1.1 --- a/gcc/gcc/ChangeLog.ggx Mon Aug 18 07:46:30 2008 -0700
1.2 +++ b/gcc/gcc/ChangeLog.ggx Wed Aug 20 11:54:09 2008 -0700
1.3 @@ -1,3 +1,21 @@
1.4 +2008-08-20 Anthony Green <green@spindazzle.org>
1.5 +
1.6 + * config/ggx/ggx.md (addsi3, subsi3, mulsi3, divsi3, udivsi3,
1.7 + modsi3, umodsi3, andsi3, xorsi3, iorsi3): Two operand instruction.
1.8 +
1.9 + * config/ggx/ggx.h (REGISTER_NAMES): Add new registers.
1.10 + (FIRST_PSEUDO_REGISTER): Ditto.
1.11 + (REG_CLASS_CONTENTS): Ditto.
1.12 + (FIXED_REGISTERS): Ditto.
1.13 + (CALL_USED_REGISTERS): Ditto.
1.14 + (REGNO_REG_CLASS): Ditto.
1.15 + (FRAME_POINTER_REGNUM): Ditto.
1.16 + (ARG_POINTER_REGNUM): Ditto.
1.17 +
1.18 + * config/ggx/ggx.c (ggx_print_operand): Handle larger number of registers.
1.19 + (ggx_expand_prologue): Ditto.
1.20 + (ggx_expand_epilogue): Ditto.
1.21 +
1.22 2008-05-05 Anthony Green <green@spindazzle.org>
1.23
1.24 * config/ggx/ggx.h (GO_IF_LEGITIMATE_ADDRESS): Revert
2.1 --- a/gcc/gcc/config/ggx/ggx.c Mon Aug 18 07:46:30 2008 -0700
2.2 +++ b/gcc/gcc/config/ggx/ggx.c Wed Aug 20 11:54:09 2008 -0700
2.3 @@ -142,7 +142,7 @@
2.4 switch (GET_CODE (operand))
2.5 {
2.6 case REG:
2.7 - if (REGNO (operand) > 7)
2.8 + if (REGNO (operand) > 15)
2.9 internal_error ("internal error: bad register: %d", REGNO (operand));
2.10 fprintf (file, "%s", reg_names[REGNO (operand)]);
2.11 return;
2.12 @@ -286,9 +286,9 @@
2.13
2.14 if (size_for_adjusting_sp > 0)
2.15 {
2.16 - insn = emit_insn (gen_movsi (gen_rtx_REG (Pmode, 7), GEN_INT (-size_for_adjusting_sp)));
2.17 + insn = emit_insn (gen_movsi (gen_rtx_REG (Pmode, 15), GEN_INT (-size_for_adjusting_sp)));
2.18 RTX_FRAME_RELATED_P (insn) = 1;
2.19 - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, gen_rtx_REG (Pmode, 7)));
2.20 + insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, gen_rtx_REG (Pmode, 15)));
2.21 RTX_FRAME_RELATED_P (insn) = 1;
2.22 }
2.23 }
2.24 @@ -301,9 +301,10 @@
2.25
2.26 if (ggx_callee_saved_reg_size != 0)
2.27 {
2.28 - insn = emit_insn (gen_movsi (gen_rtx_REG (Pmode, 7), GEN_INT (-ggx_callee_saved_reg_size)));
2.29 + insn = emit_insn (gen_movsi (gen_rtx_REG (Pmode, 15), GEN_INT (-ggx_callee_saved_reg_size)));
2.30 RTX_FRAME_RELATED_P (insn) = 1;
2.31 - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, hard_frame_pointer_rtx, gen_rtx_REG (Pmode, 7)));
2.32 + insn = emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
2.33 + insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, gen_rtx_REG (Pmode, 15)));
2.34 RTX_FRAME_RELATED_P (insn) = 1;
2.35
2.36 for (regno = FIRST_PSEUDO_REGISTER; regno > 0; --regno)
3.1 --- a/gcc/gcc/config/ggx/ggx.h Mon Aug 18 07:46:30 2008 -0700
3.2 +++ b/gcc/gcc/config/ggx/ggx.h Wed Aug 20 11:54:09 2008 -0700
3.3 @@ -64,14 +64,22 @@
3.4
3.5 /* Registers...
3.6
3.7 - $fp - frame pointer
3.8 - $sp - stack pointer
3.9 - $r0 - general purpose 32-bit register.
3.10 - $r1 - general purpose 32-bit register.
3.11 - $r2 - general purpose 32-bit register.
3.12 - $r3 - general purpose 32-bit register.
3.13 - $r4 - general purpose 32-bit register.
3.14 - $r5 - general purpose 32-bit register.
3.15 + $fp - frame pointer
3.16 + $sp - stack pointer
3.17 + $r0 - general purpose 32-bit register.
3.18 + $r1 - general purpose 32-bit register.
3.19 + $r2 - general purpose 32-bit register.
3.20 + $r3 - general purpose 32-bit register.
3.21 + $r4 - general purpose 32-bit register.
3.22 + $r5 - general purpose 32-bit register.
3.23 + $r6 - general purpose 32-bit register.
3.24 + $r7 - general purpose 32-bit register.
3.25 + $r8 - general purpose 32-bit register.
3.26 + $r9 - general purpose 32-bit register.
3.27 + $r10 - general purpose 32-bit register.
3.28 + $r11 - general purpose 32-bit register.
3.29 + $r12 - general purpose 32-bit register.
3.30 + $r13 - general purpose 32-bit register.
3.31
3.32 Special Registers...
3.33
3.34 @@ -82,9 +90,11 @@
3.35 #define REGISTER_NAMES { \
3.36 "$fp", "$sp", "$r0", "$r1", \
3.37 "$r2", "$r3", "$r4", "$r5", \
3.38 + "$r6", "$r7", "$r8", "$r9", \
3.39 + "$r10", "$r11", "$r12", "$r13", \
3.40 "?fp", "?ap", "$pc", "?cc" }
3.41
3.42 -#define FIRST_PSEUDO_REGISTER 12
3.43 +#define FIRST_PSEUDO_REGISTER 20
3.44
3.45 enum reg_class
3.46 {
3.47 @@ -101,10 +111,10 @@
3.48
3.49 #define REG_CLASS_CONTENTS \
3.50 { { 0x00000000 }, /* Empty */ \
3.51 - { (1<<10)-1 }, /* $fp, $sp, $r0 to $r5, ?fp */ \
3.52 - { (1<<10) }, /* $pc */ \
3.53 - { (1<<11) }, /* ?cc */ \
3.54 - { (1<<12)-1 } /* All registers */ \
3.55 + { (1<<18)-1 }, /* $fp, $sp, $r0 to $r5, ?fp */ \
3.56 + { (1<<18) }, /* $pc */ \
3.57 + { (1<<19) }, /* ?cc */ \
3.58 + { (1<<20)-1 } /* All registers */ \
3.59 }
3.60
3.61 #define N_REG_CLASSES LIM_REG_CLASSES
3.62 @@ -118,9 +128,13 @@
3.63
3.64 #define FIXED_REGISTERS { 1, 1, 0, 0, \
3.65 0, 0, 0, 0, \
3.66 + 0, 0, 0, 0, \
3.67 + 0, 0, 0, 0, \
3.68 1, 1, 1, 1 }
3.69
3.70 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
3.71 + 0, 0, 0, 0, \
3.72 + 0, 0, 0, 0, \
3.73 0, 0, 0, 1, \
3.74 1, 1, 1, 1 }
3.75
3.76 @@ -135,8 +149,8 @@
3.77
3.78 /* A C expression whose value is a register class containing hard
3.79 register REGNO. */
3.80 -#define REGNO_REG_CLASS(R) ((R < 10) ? GENERAL_REGS : \
3.81 - (R == 11? CC_REG : SPECIAL_REGS))
3.82 +#define REGNO_REG_CLASS(R) ((R < 18) ? GENERAL_REGS : \
3.83 + (R == 19? CC_REG : SPECIAL_REGS))
3.84
3.85 /* A C expression for the number of consecutive hard registers,
3.86 starting at register number REGNO, required to hold a value of mode
3.87 @@ -378,11 +392,11 @@
3.88
3.89 /* The register number of the frame pointer register, which is used to
3.90 access automatic variables in the stack frame. */
3.91 -#define FRAME_POINTER_REGNUM 8
3.92 +#define FRAME_POINTER_REGNUM 16
3.93
3.94 /* The register number of the arg pointer register, which is used to
3.95 access the function's argument list. */
3.96 -#define ARG_POINTER_REGNUM 9
3.97 +#define ARG_POINTER_REGNUM 17
3.98
3.99 /* If the static chain is passed in memory, these macros provide rtx
3.100 giving 'mem' expressions that denote where they are stored.
4.1 --- a/gcc/gcc/config/ggx/ggx.md Mon Aug 18 07:46:30 2008 -0700
4.2 +++ b/gcc/gcc/config/ggx/ggx.md Wed Aug 20 11:54:09 2008 -0700
4.3 @@ -15,58 +15,58 @@
4.4 (define_insn "addsi3"
4.5 [(set (match_operand:SI 0 "register_operand" "=r")
4.6 (plus:SI
4.7 - (match_operand:SI 1 "register_operand" "r")
4.8 + (match_operand:SI 1 "register_operand" "0")
4.9 (match_operand:SI 2 "general_operand" "r")))]
4.10 ""
4.11 - "add.l %0, %1, %2")
4.12 + "add.l %0, %2")
4.13
4.14 (define_insn "subsi3"
4.15 [(set (match_operand:SI 0 "register_operand" "=r")
4.16 (minus:SI
4.17 - (match_operand:SI 1 "register_operand" "r")
4.18 + (match_operand:SI 1 "register_operand" "0")
4.19 (match_operand:SI 2 "general_operand" "r")))]
4.20 ""
4.21 - "sub.l %0, %1, %2")
4.22 + "sub.l %0, %2")
4.23
4.24 (define_insn "mulsi3"
4.25 [(set (match_operand:SI 0 "register_operand" "=r")
4.26 (mult:SI
4.27 - (match_operand:SI 1 "register_operand" "r")
4.28 + (match_operand:SI 1 "register_operand" "0")
4.29 (match_operand:SI 2 "general_operand" "r")))]
4.30 ""
4.31 - "mul.l %0, %1, %2")
4.32 + "mul.l %0, %2")
4.33
4.34 (define_insn "divsi3"
4.35 [(set (match_operand:SI 0 "register_operand" "=r")
4.36 (div:SI
4.37 - (match_operand:SI 1 "register_operand" "r")
4.38 + (match_operand:SI 1 "register_operand" "0")
4.39 (match_operand:SI 2 "general_operand" "r")))]
4.40 ""
4.41 - "div.l %0, %1, %2")
4.42 + "div.l %0, %2")
4.43
4.44 (define_insn "udivsi3"
4.45 [(set (match_operand:SI 0 "register_operand" "=r")
4.46 (udiv:SI
4.47 - (match_operand:SI 1 "register_operand" "r")
4.48 + (match_operand:SI 1 "register_operand" "0")
4.49 (match_operand:SI 2 "general_operand" "r")))]
4.50 ""
4.51 - "udiv.l %0, %1, %2")
4.52 + "udiv.l %0, %2")
4.53
4.54 (define_insn "modsi3"
4.55 [(set (match_operand:SI 0 "register_operand" "=r")
4.56 (mod:SI
4.57 - (match_operand:SI 1 "register_operand" "r")
4.58 + (match_operand:SI 1 "register_operand" "0")
4.59 (match_operand:SI 2 "general_operand" "r")))]
4.60 ""
4.61 - "mod.l %0, %1, %2")
4.62 + "mod.l %0, %2")
4.63
4.64 (define_insn "umodsi3"
4.65 [(set (match_operand:SI 0 "register_operand" "=r")
4.66 (umod:SI
4.67 - (match_operand:SI 1 "register_operand" "r")
4.68 + (match_operand:SI 1 "register_operand" "0")
4.69 (match_operand:SI 2 "general_operand" "r")))]
4.70 ""
4.71 - "umod.l %0, %1, %2")
4.72 + "umod.l %0, %2")
4.73
4.74 ;; -------------------------------------------------------------------------
4.75 ;; Unary arithmetic instructions
4.76 @@ -90,29 +90,29 @@
4.77
4.78 (define_insn "andsi3"
4.79 [(set (match_operand:SI 0 "register_operand" "=r")
4.80 - (and:SI (match_operand:SI 1 "register_operand" "r")
4.81 + (and:SI (match_operand:SI 1 "register_operand" "0")
4.82 (match_operand:SI 2 "register_operand" "r")))]
4.83 ""
4.84 {
4.85 - return "and %0, %1, %2";
4.86 + return "and %0, %2";
4.87 })
4.88
4.89 (define_insn "xorsi3"
4.90 [(set (match_operand:SI 0 "register_operand" "=r")
4.91 - (xor:SI (match_operand:SI 1 "register_operand" "r")
4.92 + (xor:SI (match_operand:SI 1 "register_operand" "0")
4.93 (match_operand:SI 2 "register_operand" "r")))]
4.94 ""
4.95 {
4.96 - return "xor %0, %1, %2";
4.97 + return "xor %0, %2";
4.98 })
4.99
4.100 (define_insn "iorsi3"
4.101 [(set (match_operand:SI 0 "register_operand" "=r")
4.102 - (ior:SI (match_operand:SI 1 "register_operand" "r")
4.103 + (ior:SI (match_operand:SI 1 "register_operand" "0")
4.104 (match_operand:SI 2 "register_operand" "r")))]
4.105 ""
4.106 {
4.107 - return "or %0, %1, %2";
4.108 + return "or %0, %2";
4.109 })
4.110
4.111 ;; -------------------------------------------------------------------------
5.1 --- a/src/gas/ChangeLog.ggx Mon Aug 18 07:46:30 2008 -0700
5.2 +++ b/src/gas/ChangeLog.ggx Wed Aug 20 11:54:09 2008 -0700
5.3 @@ -1,3 +1,9 @@
5.4 +2008-08-20 Anthony Green <green@spindazzle.org>
5.5 +
5.6 + * config/tc-ggx.c (md_assemble): Handle new instruction encodings.
5.7 + (parse_register_operand): Parse register operands from $r6 to
5.8 + $r13.
5.9 +
5.10 2008-03-20 Anthony Green <green@spindazzle.org>
5.11
5.12 * config/tc-ggx.c (md_assemble): Add GGX_F1_A support.
6.1 --- a/src/gas/config/tc-ggx.c Mon Aug 18 07:46:30 2008 -0700
6.2 +++ b/src/gas/config/tc-ggx.c Wed Aug 20 11:54:09 2008 -0700
6.3 @@ -109,12 +109,21 @@
6.4 if (s[1] == 'r')
6.5 {
6.6 reg = s[2] - '0';
6.7 - if ((reg < 0) || (reg > 5))
6.8 + if ((reg < 0) || (reg > 9))
6.9 {
6.10 as_bad ("illegal register number");
6.11 ignore_rest_of_line ();
6.12 return -1;
6.13 }
6.14 + if (reg == 1)
6.15 + {
6.16 + int r2 = s[3] - '0';
6.17 + if ((r2 >= 0) && (r2 <= 3))
6.18 + {
6.19 + reg = 10 + r2;
6.20 + *ptr += 1;
6.21 + }
6.22 + }
6.23 }
6.24 else
6.25 {
6.26 @@ -176,7 +185,7 @@
6.27 switch (opcode->itype)
6.28 {
6.29 case GGX_F1_AB:
6.30 - iword = opcode->opcode << 9;
6.31 + iword = opcode->opcode << 8;
6.32 while (ISSPACE (*op_end))
6.33 op_end++;
6.34 {
6.35 @@ -186,29 +195,7 @@
6.36 as_warn ("expecting comma delimeted register operands");
6.37 op_end++;
6.38 src = parse_register_operand (&op_end);
6.39 - iword += (dest << 6) + (src << 3);
6.40 - while (ISSPACE (*op_end))
6.41 - op_end++;
6.42 - if (*op_end != 0)
6.43 - as_warn ("extra stuff on line ignored");
6.44 - }
6.45 - break;
6.46 - case GGX_F1_ABC:
6.47 - iword = opcode->opcode << 9;
6.48 - while (ISSPACE (*op_end))
6.49 - op_end++;
6.50 - {
6.51 - int a, b, c;
6.52 - a = parse_register_operand (&op_end);
6.53 - if (*op_end != ',')
6.54 - as_warn ("expecting comma delimeted register operands");
6.55 - op_end++;
6.56 - b = parse_register_operand (&op_end);
6.57 - if (*op_end != ',')
6.58 - as_warn ("expecting comma delimeted register operands");
6.59 - op_end++;
6.60 - c = parse_register_operand (&op_end);
6.61 - iword += (a << 6) + (b << 3) + c;
6.62 + iword += (dest << 4) + src;
6.63 while (ISSPACE (*op_end))
6.64 op_end++;
6.65 if (*op_end != 0)
6.66 @@ -216,7 +203,7 @@
6.67 }
6.68 break;
6.69 case GGX_F1_A4:
6.70 - iword = opcode->opcode << 9;
6.71 + iword = opcode->opcode << 8;
6.72 while (ISSPACE (*op_end))
6.73 op_end++;
6.74 {
6.75 @@ -228,7 +215,7 @@
6.76 while (ISSPACE (*op_end))
6.77 op_end++;
6.78
6.79 - iword += (regnum << 6);
6.80 + iword += (regnum << 4);
6.81
6.82 if (*op_end != ',')
6.83 {
6.84 @@ -249,7 +236,7 @@
6.85 }
6.86 break;
6.87 case GGX_F1_4:
6.88 - iword = opcode->opcode << 9;
6.89 + iword = opcode->opcode << 8;
6.90 while (ISSPACE (*op_end))
6.91 op_end++;
6.92 {
6.93 @@ -267,14 +254,14 @@
6.94 }
6.95 break;
6.96 case GGX_F1_NARG:
6.97 - iword = opcode->opcode << 9;
6.98 + iword = opcode->opcode << 8;
6.99 while (ISSPACE (*op_end))
6.100 op_end++;
6.101 if (*op_end != 0)
6.102 as_warn ("extra stuff on line ignored");
6.103 break;
6.104 case GGX_F1_A:
6.105 - iword = opcode->opcode << 9;
6.106 + iword = opcode->opcode << 8;
6.107 while (ISSPACE (*op_end))
6.108 op_end++;
6.109 {
6.110 @@ -284,11 +271,11 @@
6.111 op_end++;
6.112 if (*op_end != 0)
6.113 as_warn ("extra stuff on line ignored");
6.114 - iword += (reg << 6);
6.115 + iword += (reg << 4);
6.116 }
6.117 break;
6.118 case GGX_F1_ABi:
6.119 - iword = opcode->opcode << 9;
6.120 + iword = opcode->opcode << 8;
6.121 while (ISSPACE (*op_end))
6.122 op_end++;
6.123 {
6.124 @@ -312,7 +299,7 @@
6.125 return;
6.126 }
6.127 op_end++;
6.128 - iword += (a << 6) + (b << 3);
6.129 + iword += (a << 4) + b;
6.130 while (ISSPACE (*op_end))
6.131 op_end++;
6.132 if (*op_end != 0)
6.133 @@ -320,7 +307,7 @@
6.134 }
6.135 break;
6.136 case GGX_F1_AiB:
6.137 - iword = opcode->opcode << 9;
6.138 + iword = opcode->opcode << 8;
6.139 while (ISSPACE (*op_end))
6.140 op_end++;
6.141 {
6.142 @@ -344,7 +331,7 @@
6.143 as_warn ("expecting comma delimeted register operands");
6.144 op_end++;
6.145 b = parse_register_operand (&op_end);
6.146 - iword += (a << 6) + (b << 3);
6.147 + iword += (a << 4) + b;
6.148 while (ISSPACE (*op_end))
6.149 op_end++;
6.150 if (*op_end != 0)
6.151 @@ -352,7 +339,7 @@
6.152 }
6.153 break;
6.154 case GGX_F1_4A:
6.155 - iword = opcode->opcode << 9;
6.156 + iword = opcode->opcode << 8;
6.157 while (ISSPACE (*op_end))
6.158 op_end++;
6.159 {
6.160 @@ -383,11 +370,11 @@
6.161 if (*op_end != 0)
6.162 as_warn ("extra stuff on line ignored");
6.163
6.164 - iword += (a << 6);
6.165 + iword += (a << 4);
6.166 }
6.167 break;
6.168 case GGX_F1_ABi4:
6.169 - iword = opcode->opcode << 9;
6.170 + iword = opcode->opcode << 8;
6.171 while (ISSPACE (*op_end))
6.172 op_end++;
6.173 {
6.174 @@ -437,11 +424,11 @@
6.175 if (*op_end != 0)
6.176 as_warn ("extra stuff on line ignored");
6.177
6.178 - iword += (a << 6) + (b << 3);
6.179 + iword += (a << 4) + b;
6.180 }
6.181 break;
6.182 case GGX_F1_AiB4:
6.183 - iword = opcode->opcode << 9;
6.184 + iword = opcode->opcode << 8;
6.185 while (ISSPACE (*op_end))
6.186 op_end++;
6.187 {
6.188 @@ -491,7 +478,7 @@
6.189 if (*op_end != 0)
6.190 as_warn ("extra stuff on line ignored");
6.191
6.192 - iword += (a << 6) + (b << 3);
6.193 + iword += (a << 4) + b;
6.194 }
6.195 break;
6.196 case GGX_F2_NARG:
7.1 --- a/src/include/opcode/ggx.h Mon Aug 18 07:46:30 2008 -0700
7.2 +++ b/src/include/opcode/ggx.h Wed Aug 20 11:54:09 2008 -0700
7.3 @@ -23,7 +23,6 @@
7.4 Some have no arguments (GGX_F1_NARG)
7.5 Some only use the A operand (GGX_F1_A)
7.6 Some use A and B registers (GGX_F1_AB)
7.7 - Some use A, B and C registers (GGX_F1_ABC)
7.8 Some use A and consume a 4 byte immediate value (GGX_F1_A4)
7.9 Some use just a 4 byte immediate value (GGX_F1_4)
7.10 Some use B and an indirect A (GGX_F1_AiB)
7.11 @@ -41,7 +40,7 @@
7.12 #define GGX_F1_NARG 0x100
7.13 #define GGX_F1_A 0x101
7.14 #define GGX_F1_AB 0x102
7.15 -#define GGX_F1_ABC 0x103
7.16 +// #define GGX_F1_ABC 0x103
7.17 #define GGX_F1_A4 0x104
7.18 #define GGX_F1_4 0x105
7.19 #define GGX_F1_AiB 0x106
8.1 --- a/src/opcodes/ChangeLog.ggx Mon Aug 18 07:46:30 2008 -0700
8.2 +++ b/src/opcodes/ChangeLog.ggx Wed Aug 20 11:54:09 2008 -0700
8.3 @@ -1,3 +1,11 @@
8.4 +2008-08-20 Anthony Green <green@redhat.com>
8.5 +
8.6 + * ggx-dis.c (reg_names): Add new registers.
8.7 + (print_insn_ggx): No more three operand instructions.
8.8 + (OP_A, OP_B): Tweak for 4-bit operands.
8.9 + (OP_C): Remove. No more third operand.
8.10 + * ggx-opc.c (ggx_form1_opc_info): Switch to two operand instructions.
8.11 +
8.12 2008-04-12 Anthony Green <green@spindazzle.org>
8.13
8.14 * ggx-opc.c (ggx_form1_opc_info): Add brk.
9.1 --- a/src/opcodes/ggx-dis.c Mon Aug 18 07:46:30 2008 -0700
9.2 +++ b/src/opcodes/ggx-dis.c Wed Aug 20 11:54:09 2008 -0700
9.3 @@ -31,12 +31,12 @@
9.4 static void *stream;
9.5
9.6 /* Macros to extract operands from the instruction word. */
9.7 -#define OP_A(i) ((i >> 6) & 0x7)
9.8 -#define OP_B(i) ((i >> 3) & 0x7)
9.9 -#define OP_C(i) (i & 0x7)
9.10 +#define OP_A(i) ((i >> 4) & 0xf)
9.11 +#define OP_B(i) (i & 0xf)
9.12
9.13 -static const char *reg_names[8] =
9.14 - { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5" };
9.15 +static const char *reg_names[16] =
9.16 + { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
9.17 + "$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
9.18
9.19 int
9.20 print_insn_ggx (bfd_vma addr, struct disassemble_info *info)
9.21 @@ -57,7 +57,7 @@
9.22 if ((iword & (1<<15)) == 0)
9.23 {
9.24 /* Extract the Form 1 opcode. */
9.25 - opcode = &ggx_form1_opc_info[iword >> 9];
9.26 + opcode = &ggx_form1_opc_info[iword >> 8];
9.27 switch (opcode->itype)
9.28 {
9.29 case GGX_F1_NARG:
9.30 @@ -72,12 +72,6 @@
9.31 reg_names[OP_A(iword)],
9.32 reg_names[OP_B(iword)]);
9.33 break;
9.34 - case GGX_F1_ABC:
9.35 - fpr (stream, "%s\t%s, %s, %s", opcode->name,
9.36 - reg_names[OP_A(iword)],
9.37 - reg_names[OP_B(iword)],
9.38 - reg_names[OP_C(iword)]);
9.39 - break;
9.40 case GGX_F1_A4:
9.41 {
9.42 unsigned imm;
10.1 --- a/src/opcodes/ggx-opc.c Mon Aug 18 07:46:30 2008 -0700
10.2 +++ b/src/opcodes/ggx-opc.c Wed Aug 20 11:54:09 2008 -0700
10.3 @@ -27,13 +27,12 @@
10.4
10.5 FORM 1 instructions start with a 0 bit...
10.6
10.7 - 0ooooooaaabbbccc
10.8 + 0oooooooaaaabbbb
10.9 0 F
10.10
10.11 - oooooo - form 1 opcode number
10.12 - aaa - operand A
10.13 - bbb - operand B
10.14 - ccc - operand C
10.15 + ooooooo - form 1 opcode number
10.16 + aaaa - operand A
10.17 + bbbb - operand B
10.18
10.19 FORM 2 instructions start with a 1 bit...
10.20
10.21 @@ -51,7 +50,7 @@
10.22 { 0x01, GGX_F1_AB, "mov" },
10.23 { 0x02, GGX_F1_4, "jsra" },
10.24 { 0x03, GGX_F1_NARG, "ret" },
10.25 - { 0x04, GGX_F1_ABC, "add.l" },
10.26 + { 0x04, GGX_F1_AB, "add.l" },
10.27 { 0x05, GGX_F1_AB, "push" },
10.28 { 0x06, GGX_F1_AB, "pop" },
10.29 { 0x07, GGX_F1_A4, "lda.l" },
10.30 @@ -84,21 +83,21 @@
10.31 { 0x22, GGX_F1_AiB, "st.s" },
10.32 { 0x23, GGX_F1_4A, "sta.s" },
10.33 { 0x24, GGX_F1_A, "jmp" },
10.34 - { 0x25, GGX_F1_ABC, "and" },
10.35 + { 0x25, GGX_F1_AB, "and" },
10.36 { 0x26, GGX_F1_AB, "lshr" },
10.37 { 0x27, GGX_F1_AB, "ashl" },
10.38 - { 0x28, GGX_F1_ABC, "sub.l" },
10.39 + { 0x28, GGX_F1_AB, "sub.l" },
10.40 { 0x29, GGX_F1_AB, "neg" },
10.41 - { 0x2a, GGX_F1_ABC, "or" },
10.42 + { 0x2a, GGX_F1_AB, "or" },
10.43 { 0x2b, GGX_F1_AB, "not" },
10.44 { 0x2c, GGX_F1_AB, "ashr" },
10.45 - { 0x2d, GGX_F1_ABC, "xor" },
10.46 - { 0x2e, GGX_F1_ABC, "mul.l" },
10.47 + { 0x2d, GGX_F1_AB, "xor" },
10.48 + { 0x2e, GGX_F1_AB, "mul.l" },
10.49 { 0x2f, GGX_F1_4, "swi" },
10.50 - { 0x30, GGX_F1_ABC, "div.l" },
10.51 - { 0x31, GGX_F1_ABC, "udiv.l" },
10.52 - { 0x32, GGX_F1_ABC, "mod.l" },
10.53 - { 0x33, GGX_F1_ABC, "umod.l" },
10.54 + { 0x30, GGX_F1_AB, "div.l" },
10.55 + { 0x31, GGX_F1_AB, "udiv.l" },
10.56 + { 0x32, GGX_F1_AB, "mod.l" },
10.57 + { 0x33, GGX_F1_AB, "umod.l" },
10.58 { 0x34, GGX_F1_NARG, "brk" },
10.59 { 0x35, GGX_F1_NARG, "bad" },
10.60 { 0x36, GGX_F1_NARG, "bad" },
11.1 --- a/src/sim/ggx/ChangeLog Mon Aug 18 07:46:30 2008 -0700
11.2 +++ b/src/sim/ggx/ChangeLog Wed Aug 20 11:54:09 2008 -0700
11.3 @@ -1,3 +1,12 @@
11.4 +2008-08-20 Anthony Green <green@spindazzle.org>
11.5 +
11.6 + * interp.c (TRACE): Add new tracing infrastructure.
11.7 + (sim_resume): Use it.
11.8 + (reg_names): Add new registers.
11.9 + (NUM_GGX_REGS): New registers.
11.10 + (PC_REGNO): New registers.
11.11 + (sim_resume): New instruction encodings.
11.12 +
11.13 2008-08-16 Anthony Green <green@spindazzle.org>
11.14
11.15 * interp.c (sim_resume): Add SYS_read, and fix SYS_open and SYS_write.
12.1 --- a/src/sim/ggx/interp.c Mon Aug 18 07:46:30 2008 -0700
12.2 +++ b/src/sim/ggx/interp.c Wed Aug 20 11:54:09 2008 -0700
12.3 @@ -82,8 +82,9 @@
12.4 }
12.5
12.6 /* ggx register names. */
12.7 -static const char *reg_names[8] =
12.8 - { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5" };
12.9 +static const char *reg_names[16] =
12.10 + { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
12.11 + "$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
12.12
12.13 /* The machine state.
12.14
12.15 @@ -94,8 +95,8 @@
12.16 data in native order improves the performance of the simulator.
12.17 Simulation speed is deemed more important. */
12.18
12.19 -#define NUM_GGX_REGS 9 /* Including PC */
12.20 -#define PC_REGNO 8
12.21 +#define NUM_GGX_REGS 17 /* Including PC */
12.22 +#define PC_REGNO 16
12.23
12.24 /* The ordering of the ggx_regset structure is matched in the
12.25 gdb/config/ggx/tm-ggx.h file in the REGISTER_NAMES macro. */
12.26 @@ -385,6 +386,7 @@
12.27 return hflags;
12.28 }
12.29
12.30 +#define TRACE(str) if (tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);
12.31
12.32 static int tracing = 0;
12.33
12.34 @@ -407,12 +409,6 @@
12.35 /* Run instructions here. */
12.36 do
12.37 {
12.38 - if (tracing)
12.39 - {
12.40 - fwrite(&pc, 4, 1, tracefile);
12.41 - fwrite(cpu.asints, NUM_GGX_REGS + 1 + 2, 4, tracefile);
12.42 - }
12.43 -
12.44 opc = pc;
12.45
12.46 /* Fetch the instruction at pc. */
12.47 @@ -429,13 +425,13 @@
12.48 else
12.49 {
12.50 /* This is a Form 1 instruction. */
12.51 - int opcode = inst >> 9;
12.52 + int opcode = inst >> 8;
12.53 switch (opcode)
12.54 {
12.55 case 0x00: /* ldi.l (immediate) */
12.56 {
12.57 - int reg = (inst >> 6) & 0x7;
12.58 -
12.59 + int reg = (inst >> 4) & 0xf;
12.60 + TRACE("ldi.l");
12.61 unsigned int val = EXTRACT_WORD(&(memory[pc + 2]));
12.62 cpu.asregs.regs[reg] = val;
12.63 pc += 4;
12.64 @@ -443,8 +439,9 @@
12.65 break;
12.66 case 0x01: /* mov (register-to-register) */
12.67 {
12.68 - int dest = (inst >> 6) & 0x7;
12.69 - int src = (inst >> 3) & 0x7;
12.70 + int dest = (inst >> 4) & 0xf;
12.71 + int src = (inst ) & 0xf;
12.72 + TRACE("mov");
12.73 cpu.asregs.regs[dest] = cpu.asregs.regs[src];
12.74 }
12.75 break;
12.76 @@ -452,7 +449,7 @@
12.77 {
12.78 unsigned int fn = EXTRACT_WORD(&(memory[pc + 2]));
12.79 unsigned int sp = cpu.asregs.regs[1];
12.80 -
12.81 + TRACE("jsra");
12.82 /* Save a slot for the static chain. */
12.83 sp -= 4;
12.84
12.85 @@ -473,6 +470,8 @@
12.86 case 0x03: /* ret */
12.87 {
12.88 unsigned int sp = cpu.asregs.regs[0];
12.89 +
12.90 + TRACE("ret");
12.91
12.92 /* Pop the frame pointer. */
12.93 cpu.asregs.regs[0] = rlat (opc, sp);
12.94 @@ -491,69 +490,76 @@
12.95 break;
12.96 case 0x04: /* add.l */
12.97 {
12.98 - int a = (inst >> 6) & 0x7;
12.99 - int b = (inst >> 3) & 0x7;
12.100 - int c = inst & 0x7;
12.101 + int a = (inst >> 4) & 0xf;
12.102 + int b = inst & 0xf;
12.103 + unsigned av = cpu.asregs.regs[a];
12.104 unsigned bv = cpu.asregs.regs[b];
12.105 - unsigned cv = cpu.asregs.regs[c];
12.106 - cpu.asregs.regs[a] = bv + cv;
12.107 + TRACE("add.l");
12.108 + cpu.asregs.regs[a] = av + bv;
12.109 }
12.110 break;
12.111 case 0x05: /* push */
12.112 {
12.113 - int a = (inst >> 6) & 0x7;
12.114 - int b = (inst >> 3) & 0x7;
12.115 + int a = (inst >> 4) & 0xf;
12.116 + int b = inst & 0xf;
12.117 int sp = cpu.asregs.regs[a] - 4;
12.118 + TRACE("push");
12.119 wlat (opc, sp, cpu.asregs.regs[b]);
12.120 cpu.asregs.regs[a] = sp;
12.121 }
12.122 break;
12.123 case 0x06: /* pop */
12.124 {
12.125 - int a = (inst >> 6) & 0x7;
12.126 - int b = (inst >> 3) & 0x7;
12.127 + int a = (inst >> 4) & 0xf;
12.128 + int b = inst & 0xf;
12.129 int sp = cpu.asregs.regs[a];
12.130 + TRACE("pop");
12.131 cpu.asregs.regs[b] = rlat (opc, sp);
12.132 cpu.asregs.regs[a] = sp + 4;
12.133 }
12.134 break;
12.135 case 0x07: /* lda.l */
12.136 {
12.137 - int reg = (inst >> 6) & 0x7;
12.138 + int reg = (inst >> 4) & 0xf;
12.139 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
12.140 + TRACE("lda.l");
12.141 cpu.asregs.regs[reg] = rlat (opc, addr);
12.142 pc += 4;
12.143 }
12.144 break;
12.145 case 0x08: /* sta.l */
12.146 {
12.147 - int reg = (inst >> 6) & 0x7;
12.148 + int reg = (inst >> 4) & 0xf;
12.149 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
12.150 + TRACE("sta.l");
12.151 wlat (opc, addr, cpu.asregs.regs[reg]);
12.152 pc += 4;
12.153 }
12.154 break;
12.155 case 0x09: /* ld.l (register indirect) */
12.156 {
12.157 - int src = (inst >> 3) & 0x7;
12.158 - int dest = (inst >> 6) & 0x7;
12.159 + int src = inst & 0xf;
12.160 + int dest = (inst >> 4) & 0xf;
12.161 int xv;
12.162 + TRACE("ld.l");
12.163 xv = cpu.asregs.regs[src];
12.164 cpu.asregs.regs[dest] = rlat (opc, xv);
12.165 }
12.166 break;
12.167 case 0x0a: /* st.l */
12.168 {
12.169 - int dest = (inst >> 6) & 0x7;
12.170 - int val = (inst >> 3) & 0x7;
12.171 + int dest = (inst >> 4) & 0xf;
12.172 + int val = inst & 0xf;
12.173 + TRACE("st.l");
12.174 wlat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
12.175 }
12.176 break;
12.177 case 0x0b: /* ldo.l */
12.178 {
12.179 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
12.180 - int a = (inst >> 6) & 0x7;
12.181 - int b = (inst >> 3) & 0x7;
12.182 + int a = (inst >> 4) & 0xf;
12.183 + int b = inst & 0xf;
12.184 + TRACE("ldo.l");
12.185 addr += cpu.asregs.regs[b];
12.186 cpu.asregs.regs[a] = rlat(opc, addr);
12.187 pc += 4;
12.188 @@ -562,8 +568,9 @@
12.189 case 0x0c: /* sto.w */
12.190 {
12.191 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
12.192 - int a = (inst >> 6) & 0x7;
12.193 - int b = (inst >> 3) & 0x7;
12.194 + int a = (inst >> 4) & 0xf;
12.195 + int b = inst & 0xf;
12.196 + TRACE("sto.w");
12.197 addr += cpu.asregs.regs[a];
12.198 wlat(opc, addr, cpu.asregs.regs[b]);
12.199 pc += 4;
12.200 @@ -571,12 +578,14 @@
12.201 break;
12.202 case 0x0d: /* cmp */
12.203 {
12.204 - int a = (inst >> 6) & 0x7;
12.205 - int b = (inst >> 3) & 0x7;
12.206 + int a = (inst >> 4) & 0xf;
12.207 + int b = inst & 0xf;
12.208 int cc = 0;
12.209 int va = cpu.asregs.regs[a];
12.210 int vb = cpu.asregs.regs[b];
12.211
12.212 + TRACE("cmp");
12.213 +
12.214 if (va == vb)
12.215 cc = CC_EQ;
12.216 else
12.217 @@ -593,6 +602,7 @@
12.218 case 0x0e: /* beq */
12.219 {
12.220 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.221 + TRACE("beq");
12.222 if (cpu.asregs.cc & CC_EQ)
12.223 {
12.224 pc = tgt - 2;
12.225 @@ -604,6 +614,7 @@
12.226 case 0x0f: /* bne */
12.227 {
12.228 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.229 + TRACE("bne");
12.230 if (! (cpu.asregs.cc & CC_EQ))
12.231 {
12.232 pc = tgt - 2;
12.233 @@ -615,6 +626,7 @@
12.234 case 0x10: /* blt */
12.235 {
12.236 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.237 + TRACE("blt");
12.238 if (cpu.asregs.cc & CC_LT)
12.239 {
12.240 pc = tgt - 2;
12.241 @@ -626,6 +638,7 @@
12.242 case 0x11: /* bgt */
12.243 {
12.244 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.245 + TRACE("bgt");
12.246 if (cpu.asregs.cc & CC_GT)
12.247 {
12.248 pc = tgt - 2;
12.249 @@ -637,6 +650,7 @@
12.250 case 0x12: /* bltu */
12.251 {
12.252 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.253 + TRACE("bltu");
12.254 if (cpu.asregs.cc & CC_LTU)
12.255 {
12.256 pc = tgt - 2;
12.257 @@ -648,6 +662,7 @@
12.258 case 0x13: /* bgtu */
12.259 {
12.260 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.261 + TRACE("bgtu");
12.262 if (cpu.asregs.cc & CC_GTU)
12.263 {
12.264 pc = tgt - 2;
12.265 @@ -659,6 +674,7 @@
12.266 case 0x14: /* bge */
12.267 {
12.268 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.269 + TRACE("bge");
12.270 if ((cpu.asregs.cc & CC_GT) || (cpu.asregs.cc & CC_EQ))
12.271 {
12.272 pc = tgt - 2;
12.273 @@ -670,6 +686,7 @@
12.274 case 0x15: /* ble */
12.275 {
12.276 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.277 + TRACE("ble");
12.278 if ((cpu.asregs.cc & CC_LT) || (cpu.asregs.cc & CC_EQ))
12.279 {
12.280 pc = tgt - 2;
12.281 @@ -681,6 +698,7 @@
12.282 case 0x16: /* bgeu */
12.283 {
12.284 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.285 + TRACE("bgeu");
12.286 if ((cpu.asregs.cc & CC_GTU) || (cpu.asregs.cc & CC_EQ))
12.287 {
12.288 pc = tgt - 2;
12.289 @@ -692,6 +710,7 @@
12.290 case 0x17: /* bleu */
12.291 {
12.292 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.293 + TRACE("bleu");
12.294 if ((cpu.asregs.cc & CC_LTU) || (cpu.asregs.cc & CC_EQ))
12.295 {
12.296 pc = tgt - 2;
12.297 @@ -702,9 +721,11 @@
12.298 break;
12.299 case 0x18: /* jsr */
12.300 {
12.301 - unsigned int fn = cpu.asregs.regs[(inst >> 6) & 0x7];
12.302 + unsigned int fn = cpu.asregs.regs[(inst >> 4) & 0xf];
12.303 unsigned int sp = cpu.asregs.regs[1];
12.304
12.305 + TRACE("jsr");
12.306 +
12.307 /* Save a slot for the static chain. */
12.308 sp -= 4;
12.309
12.310 @@ -725,196 +746,214 @@
12.311 case 0x19: /* jmpa */
12.312 {
12.313 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
12.314 + TRACE("jmpa");
12.315 pc = tgt - 2;
12.316 }
12.317 break;
12.318 case 0x1a: /* ldi.b (immediate) */
12.319 {
12.320 - int reg = (inst >> 6) & 0x7;
12.321 + int reg = (inst >> 4) & 0xf;
12.322
12.323 unsigned int val = EXTRACT_WORD(&(memory[pc + 2]));
12.324 + TRACE("ldi.b");
12.325 cpu.asregs.regs[reg] = val;
12.326 pc += 4;
12.327 }
12.328 break;
12.329 case 0x1b: /* ld.b (register indirect) */
12.330 {
12.331 - int src = (inst >> 3) & 0x7;
12.332 - int dest = (inst >> 6) & 0x7;
12.333 + int src = inst & 0xf;
12.334 + int dest = (inst >> 4) & 0xf;
12.335 int xv;
12.336 + TRACE("ld.b");
12.337 xv = cpu.asregs.regs[src];
12.338 cpu.asregs.regs[dest] = rbat (opc, xv);
12.339 }
12.340 break;
12.341 case 0x1c: /* lda.b */
12.342 {
12.343 - int reg = (inst >> 6) & 0x7;
12.344 + int reg = (inst >> 4) & 0xf;
12.345 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
12.346 + TRACE("lda.b");
12.347 cpu.asregs.regs[reg] = rbat (opc, addr);
12.348 pc += 4;
12.349 }
12.350 break;
12.351 case 0x1d: /* st.b */
12.352 {
12.353 - int dest = (inst >> 6) & 0x7;
12.354 - int val = (inst >> 3) & 0x7;
12.355 + int dest = (inst >> 4) & 0xf;
12.356 + int val = inst & 0xf;
12.357 + TRACE("st.b");
12.358 wbat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
12.359 }
12.360 break;
12.361 case 0x1e: /* sta.b */
12.362 {
12.363 - int reg = (inst >> 6) & 0x7;
12.364 + int reg = (inst >> 4) & 0xf;
12.365 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
12.366 + TRACE("sta.b");
12.367 wbat (opc, addr, cpu.asregs.regs[reg]);
12.368 pc += 4;
12.369 }
12.370 break;
12.371 case 0x1f: /* ldi.s (immediate) */
12.372 {
12.373 - int reg = (inst >> 6) & 0x7;
12.374 + int reg = (inst >> 4) & 0xf;
12.375
12.376 unsigned int val = EXTRACT_WORD(&(memory[pc + 2]));
12.377 + TRACE("ldi.s");
12.378 cpu.asregs.regs[reg] = val;
12.379 pc += 4;
12.380 }
12.381 break;
12.382 case 0x20: /* ld.s (register indirect) */
12.383 {
12.384 - int src = (inst >> 3) & 0x7;
12.385 - int dest = (inst >> 6) & 0x7;
12.386 + int src = inst & 0xf;
12.387 + int dest = (inst >> 4) & 0xf;
12.388 int xv;
12.389 + TRACE("ld.s");
12.390 xv = cpu.asregs.regs[src];
12.391 cpu.asregs.regs[dest] = rsat (opc, xv);
12.392 }
12.393 break;
12.394 case 0x21: /* lda.s */
12.395 {
12.396 - int reg = (inst >> 6) & 0x7;
12.397 + int reg = (inst >> 4) & 0xf;
12.398 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
12.399 + TRACE("lda.s");
12.400 cpu.asregs.regs[reg] = rsat (opc, addr);
12.401 pc += 4;
12.402 }
12.403 break;
12.404 case 0x22: /* st.s */
12.405 {
12.406 - int dest = (inst >> 6) & 0x7;
12.407 - int val = (inst >> 3) & 0x7;
12.408 + int dest = (inst >> 4) & 0xf;
12.409 + int val = inst & 0xf;
12.410 + TRACE("st.s");
12.411 wsat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
12.412 }
12.413 break;
12.414 case 0x23: /* sta.s */
12.415 {
12.416 - int reg = (inst >> 6) & 0x7;
12.417 + int reg = (inst >> 4) & 0xf;
12.418 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
12.419 + TRACE("sta.s");
12.420 wsat (opc, addr, cpu.asregs.regs[reg]);
12.421 pc += 4;
12.422 }
12.423 break;
12.424 case 0x24: /* jmp */
12.425 {
12.426 - int reg = (inst >> 6) & 0x7;
12.427 + int reg = (inst >> 4) & 0xf;
12.428 + TRACE("jmp");
12.429 pc = cpu.asregs.regs[reg] - 2;
12.430 }
12.431 break;
12.432 case 0x25: /* and */
12.433 {
12.434 - int a = (inst >> 6) & 0x7;
12.435 - int b = (inst >> 3) & 0x7;
12.436 - int c = inst & 0x7;
12.437 - int bv, cv;
12.438 + int a = (inst >> 4) & 0xf;
12.439 + int b = inst & 0xf;
12.440 + int av, bv;
12.441 + TRACE("and");
12.442 + av = cpu.asregs.regs[a];
12.443 bv = cpu.asregs.regs[b];
12.444 - cv = cpu.asregs.regs[c];
12.445 - cpu.asregs.regs[a] = bv & cv;
12.446 + cpu.asregs.regs[a] = av & bv;
12.447 }
12.448 break;
12.449 case 0x26: /* lshr */
12.450 {
12.451 - int a = (inst >> 6) & 0x7;
12.452 - int b = (inst >> 3) & 0x7;
12.453 + int a = (inst >> 4) & 0xf;
12.454 + int b = inst & 0xf;
12.455 int av = cpu.asregs.regs[a];
12.456 int bv = cpu.asregs.regs[b];
12.457 + TRACE("lshr");
12.458 cpu.asregs.regs[a] = (unsigned) ((unsigned) av >> bv);
12.459 }
12.460 break;
12.461 case 0x27: /* ashl */
12.462 {
12.463 - int a = (inst >> 6) & 0x7;
12.464 - int b = (inst >> 3) & 0x7;
12.465 + int a = (inst >> 4) & 0xf;
12.466 + int b = inst & 0xf;
12.467 int av = cpu.asregs.regs[a];
12.468 int bv = cpu.asregs.regs[b];
12.469 + TRACE("ashl");
12.470 cpu.asregs.regs[a] = av << bv;
12.471 }
12.472 break;
12.473 case 0x28: /* sub.l */
12.474 {
12.475 - int a = (inst >> 6) & 0x7;
12.476 - int b = (inst >> 3) & 0x7;
12.477 - int c = inst & 0x7;
12.478 + int a = (inst >> 4) & 0xf;
12.479 + int b = inst & 0xf;
12.480 + unsigned av = cpu.asregs.regs[a];
12.481 unsigned bv = cpu.asregs.regs[b];
12.482 - unsigned cv = cpu.asregs.regs[c];
12.483 - cpu.asregs.regs[a] = bv - cv;
12.484 + TRACE("sub.l");
12.485 + cpu.asregs.regs[a] = av - bv;
12.486 }
12.487 break;
12.488 case 0x29: /* neg */
12.489 {
12.490 - int a = (inst >> 6) & 0x7;
12.491 - int b = (inst >> 3) & 0x7;
12.492 + int a = (inst >> 4) & 0xf;
12.493 + int b = inst & 0xf;
12.494 int bv = cpu.asregs.regs[b];
12.495 + TRACE("neg");
12.496 cpu.asregs.regs[a] = - bv;
12.497 }
12.498 break;
12.499 case 0x2a: /* or */
12.500 {
12.501 - int a = (inst >> 6) & 0x7;
12.502 - int b = (inst >> 3) & 0x7;
12.503 - int c = inst & 0x7;
12.504 - int bv, cv;
12.505 + int a = (inst >> 4) & 0xf;
12.506 + int b = inst & 0xf;
12.507 + int av, bv;
12.508 + TRACE("or");
12.509 + av = cpu.asregs.regs[a];
12.510 bv = cpu.asregs.regs[b];
12.511 - cv = cpu.asregs.regs[c];
12.512 - cpu.asregs.regs[a] = bv | cv;
12.513 + cpu.asregs.regs[a] = av | bv;
12.514 }
12.515 break;
12.516 case 0x2b: /* not */
12.517 {
12.518 - int a = (inst >> 6) & 0x7;
12.519 - int b = (inst >> 3) & 0x7;
12.520 + int a = (inst >> 4) & 0xf;
12.521 + int b = inst & 0xf;
12.522 int bv = cpu.asregs.regs[b];
12.523 + TRACE("not");
12.524 cpu.asregs.regs[a] = 0xffffffff ^ bv;
12.525 }
12.526 break;
12.527 case 0x2c: /* ashr */
12.528 {
12.529 - int a = (inst >> 6) & 0x7;
12.530 - int b = (inst >> 3) & 0x7;
12.531 + int a = (inst >> 4) & 0xf;
12.532 + int b = inst & 0xf;
12.533 int av = cpu.asregs.regs[a];
12.534 int bv = cpu.asregs.regs[b];
12.535 + TRACE("ashr");
12.536 cpu.asregs.regs[a] = av >> bv;
12.537 }
12.538 break;
12.539 case 0x2d: /* xor */
12.540 {
12.541 - int a = (inst >> 6) & 0x7;
12.542 - int b = (inst >> 3) & 0x7;
12.543 - int c = inst & 0x7;
12.544 - int bv, cv;
12.545 + int a = (inst >> 4) & 0xf;
12.546 + int b = inst & 0xf;
12.547 + int av, bv;
12.548 + TRACE("xor");
12.549 + av = cpu.asregs.regs[a];
12.550 bv = cpu.asregs.regs[b];
12.551 - cv = cpu.asregs.regs[c];
12.552 - cpu.asregs.regs[a] = bv ^ cv;
12.553 + cpu.asregs.regs[a] = av ^ bv;
12.554 }
12.555 break;
12.556 case 0x2e: /* mul.l */
12.557 {
12.558 - int a = (inst >> 6) & 0x7;
12.559 - int b = (inst >> 3) & 0x7;
12.560 - int c = inst & 0x7;
12.561 + int a = (inst >> 4) & 0xf;
12.562 + int b = inst & 0xf;
12.563 + unsigned av = cpu.asregs.regs[a];
12.564 unsigned bv = cpu.asregs.regs[b];
12.565 - unsigned cv = cpu.asregs.regs[c];
12.566 - cpu.asregs.regs[a] = bv * cv;
12.567 + TRACE("mul.l");
12.568 + cpu.asregs.regs[a] = av * bv;
12.569 }
12.570 break;
12.571 case 0x2f: /* swi */
12.572 {
12.573 unsigned int inum = EXTRACT_WORD(&memory[pc+2]);
12.574 + TRACE("swi");
12.575 switch (inum)
12.576 {
12.577 case 0x1: /* SYS_exit */
12.578 @@ -964,55 +1003,52 @@
12.579 break;
12.580 case 0x30: /* div.l */
12.581 {
12.582 - int a = (inst >> 6) & 0x7;
12.583 - int b = (inst >> 3) & 0x7;
12.584 - int c = inst & 0x7;
12.585 + int a = (inst >> 4) & 0xf;
12.586 + int b = inst & 0xf;
12.587 + int av = cpu.asregs.regs[a];
12.588 int bv = cpu.asregs.regs[b];
12.589 - int cv = cpu.asregs.regs[c];
12.590 - cpu.asregs.regs[a] = bv / cv;
12.591 + TRACE("div.l");
12.592 + cpu.asregs.regs[a] = av / bv;
12.593 }
12.594 break;
12.595 case 0x31: /* udiv.l */
12.596 {
12.597 - int a = (inst >> 6) & 0x7;
12.598 - int b = (inst >> 3) & 0x7;
12.599 - int c = inst & 0x7;
12.600 + int a = (inst >> 4) & 0xf;
12.601 + int b = inst & 0xf;
12.602 + unsigned int av = cpu.asregs.regs[a];
12.603 unsigned int bv = cpu.asregs.regs[b];
12.604 - unsigned int cv = cpu.asregs.regs[c];
12.605 - cpu.asregs.regs[a] = (bv / cv);
12.606 + TRACE("udiv.l");
12.607 + cpu.asregs.regs[a] = (av / bv);
12.608 }
12.609 break;
12.610 case 0x32: /* mod.l */
12.611 {
12.612 - int a = (inst >> 6) & 0x7;
12.613 - int b = (inst >> 3) & 0x7;
12.614 - int c = inst & 0x7;
12.615 + int a = (inst >> 4) & 0xf;
12.616 + int b = inst & 0xf;
12.617 + int av = cpu.asregs.regs[a];
12.618 int bv = cpu.asregs.regs[b];
12.619 - int cv = cpu.asregs.regs[c];
12.620 - cpu.asregs.regs[a] = bv % cv;
12.621 + TRACE("mod.l");
12.622 + cpu.asregs.regs[a] = av % bv;
12.623 }
12.624 break;
12.625 case 0x33: /* umod.l */
12.626 {
12.627 - int a = (inst >> 6) & 0x7;
12.628 - int b = (inst >> 3) & 0x7;
12.629 - int c = inst & 0x7;
12.630 + int a = (inst >> 4) & 0xf;
12.631 + int b = inst & 0xf;
12.632 + unsigned int av = cpu.asregs.regs[a];
12.633 unsigned int bv = cpu.asregs.regs[b];
12.634 - unsigned int cv = cpu.asregs.regs[c];
12.635 - cpu.asregs.regs[a] = (bv % cv);
12.636 + TRACE("umod.l");
12.637 + cpu.asregs.regs[a] = (av % bv);
12.638 }
12.639 break;
12.640 case 0x34: /* brk */
12.641 + TRACE("brk");
12.642 cpu.asregs.exception = SIGTRAP;
12.643 pc -= 2; /* Adjust pc */
12.644 break;
12.645 default:
12.646 + TRACE("SIGILL");
12.647 cpu.asregs.exception = SIGILL;
12.648 - if (tracing)
12.649 - {
12.650 - fwrite(&pc, 4, 1, tracefile);
12.651 - fwrite(cpu.asints, NUM_GGX_REGS + 1 + 2, 4, tracefile);
12.652 - }
12.653 break;
12.654 }
12.655 }
12.656 @@ -1117,7 +1153,7 @@
12.657 SIM_DESC sd;
12.658 {
12.659 if (tracefile == 0)
12.660 - tracefile = fopen("trace.dat", "wb");
12.661 + tracefile = fopen("trace.csv", "wb");
12.662
12.663 tracing = 1;
12.664