1 --- a/gcc/gcc/ChangeLog.ggx Mon Aug 18 07:46:30 2008 -0700
2 +++ b/gcc/gcc/ChangeLog.ggx Wed Aug 20 11:54:09 2008 -0700
3 @@ -1,3 +1,21 @@
4 +2008-08-20 Anthony Green <green@spindazzle.org>
5 +
6 + * config/ggx/ggx.md (addsi3, subsi3, mulsi3, divsi3, udivsi3,
7 + modsi3, umodsi3, andsi3, xorsi3, iorsi3): Two operand instruction.
8 +
9 + * config/ggx/ggx.h (REGISTER_NAMES): Add new registers.
10 + (FIRST_PSEUDO_REGISTER): Ditto.
11 + (REG_CLASS_CONTENTS): Ditto.
12 + (FIXED_REGISTERS): Ditto.
13 + (CALL_USED_REGISTERS): Ditto.
14 + (REGNO_REG_CLASS): Ditto.
15 + (FRAME_POINTER_REGNUM): Ditto.
16 + (ARG_POINTER_REGNUM): Ditto.
17 +
18 + * config/ggx/ggx.c (ggx_print_operand): Handle larger number of registers.
19 + (ggx_expand_prologue): Ditto.
20 + (ggx_expand_epilogue): Ditto.
21 +
22 2008-05-05 Anthony Green <green@spindazzle.org>
23
24 * config/ggx/ggx.h (GO_IF_LEGITIMATE_ADDRESS): Revert
1.1 --- a/gcc/gcc/config/ggx/ggx.c Mon Aug 18 07:46:30 2008 -0700
1.2 +++ b/gcc/gcc/config/ggx/ggx.c Wed Aug 20 11:54:09 2008 -0700
1.3 @@ -142,7 +142,7 @@
1.4 switch (GET_CODE (operand))
1.5 {
1.6 case REG:
1.7 - if (REGNO (operand) > 7)
1.8 + if (REGNO (operand) > 15)
1.9 internal_error ("internal error: bad register: %d", REGNO (operand));
1.10 fprintf (file, "%s", reg_names[REGNO (operand)]);
1.11 return;
1.12 @@ -286,9 +286,9 @@
1.13
1.14 if (size_for_adjusting_sp > 0)
1.15 {
1.16 - insn = emit_insn (gen_movsi (gen_rtx_REG (Pmode, 7), GEN_INT (-size_for_adjusting_sp)));
1.17 + insn = emit_insn (gen_movsi (gen_rtx_REG (Pmode, 15), GEN_INT (-size_for_adjusting_sp)));
1.18 RTX_FRAME_RELATED_P (insn) = 1;
1.19 - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, gen_rtx_REG (Pmode, 7)));
1.20 + insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, gen_rtx_REG (Pmode, 15)));
1.21 RTX_FRAME_RELATED_P (insn) = 1;
1.22 }
1.23 }
1.24 @@ -301,9 +301,10 @@
1.25
1.26 if (ggx_callee_saved_reg_size != 0)
1.27 {
1.28 - insn = emit_insn (gen_movsi (gen_rtx_REG (Pmode, 7), GEN_INT (-ggx_callee_saved_reg_size)));
1.29 + insn = emit_insn (gen_movsi (gen_rtx_REG (Pmode, 15), GEN_INT (-ggx_callee_saved_reg_size)));
1.30 RTX_FRAME_RELATED_P (insn) = 1;
1.31 - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, hard_frame_pointer_rtx, gen_rtx_REG (Pmode, 7)));
1.32 + insn = emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
1.33 + insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, gen_rtx_REG (Pmode, 15)));
1.34 RTX_FRAME_RELATED_P (insn) = 1;
1.35
1.36 for (regno = FIRST_PSEUDO_REGISTER; regno > 0; --regno)
2.1 --- a/gcc/gcc/config/ggx/ggx.h Mon Aug 18 07:46:30 2008 -0700
2.2 +++ b/gcc/gcc/config/ggx/ggx.h Wed Aug 20 11:54:09 2008 -0700
2.3 @@ -64,14 +64,22 @@
2.4
2.5 /* Registers...
2.6
2.7 - $fp - frame pointer
2.8 - $sp - stack pointer
2.9 - $r0 - general purpose 32-bit register.
2.10 - $r1 - general purpose 32-bit register.
2.11 - $r2 - general purpose 32-bit register.
2.12 - $r3 - general purpose 32-bit register.
2.13 - $r4 - general purpose 32-bit register.
2.14 - $r5 - general purpose 32-bit register.
2.15 + $fp - frame pointer
2.16 + $sp - stack pointer
2.17 + $r0 - general purpose 32-bit register.
2.18 + $r1 - general purpose 32-bit register.
2.19 + $r2 - general purpose 32-bit register.
2.20 + $r3 - general purpose 32-bit register.
2.21 + $r4 - general purpose 32-bit register.
2.22 + $r5 - general purpose 32-bit register.
2.23 + $r6 - general purpose 32-bit register.
2.24 + $r7 - general purpose 32-bit register.
2.25 + $r8 - general purpose 32-bit register.
2.26 + $r9 - general purpose 32-bit register.
2.27 + $r10 - general purpose 32-bit register.
2.28 + $r11 - general purpose 32-bit register.
2.29 + $r12 - general purpose 32-bit register.
2.30 + $r13 - general purpose 32-bit register.
2.31
2.32 Special Registers...
2.33
2.34 @@ -82,9 +90,11 @@
2.35 #define REGISTER_NAMES { \
2.36 "$fp", "$sp", "$r0", "$r1", \
2.37 "$r2", "$r3", "$r4", "$r5", \
2.38 + "$r6", "$r7", "$r8", "$r9", \
2.39 + "$r10", "$r11", "$r12", "$r13", \
2.40 "?fp", "?ap", "$pc", "?cc" }
2.41
2.42 -#define FIRST_PSEUDO_REGISTER 12
2.43 +#define FIRST_PSEUDO_REGISTER 20
2.44
2.45 enum reg_class
2.46 {
2.47 @@ -101,10 +111,10 @@
2.48
2.49 #define REG_CLASS_CONTENTS \
2.50 { { 0x00000000 }, /* Empty */ \
2.51 - { (1<<10)-1 }, /* $fp, $sp, $r0 to $r5, ?fp */ \
2.52 - { (1<<10) }, /* $pc */ \
2.53 - { (1<<11) }, /* ?cc */ \
2.54 - { (1<<12)-1 } /* All registers */ \
2.55 + { (1<<18)-1 }, /* $fp, $sp, $r0 to $r5, ?fp */ \
2.56 + { (1<<18) }, /* $pc */ \
2.57 + { (1<<19) }, /* ?cc */ \
2.58 + { (1<<20)-1 } /* All registers */ \
2.59 }
2.60
2.61 #define N_REG_CLASSES LIM_REG_CLASSES
2.62 @@ -118,9 +128,13 @@
2.63
2.64 #define FIXED_REGISTERS { 1, 1, 0, 0, \
2.65 0, 0, 0, 0, \
2.66 + 0, 0, 0, 0, \
2.67 + 0, 0, 0, 0, \
2.68 1, 1, 1, 1 }
2.69
2.70 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
2.71 + 0, 0, 0, 0, \
2.72 + 0, 0, 0, 0, \
2.73 0, 0, 0, 1, \
2.74 1, 1, 1, 1 }
2.75
2.76 @@ -135,8 +149,8 @@
2.77
2.78 /* A C expression whose value is a register class containing hard
2.79 register REGNO. */
2.80 -#define REGNO_REG_CLASS(R) ((R < 10) ? GENERAL_REGS : \
2.81 - (R == 11? CC_REG : SPECIAL_REGS))
2.82 +#define REGNO_REG_CLASS(R) ((R < 18) ? GENERAL_REGS : \
2.83 + (R == 19? CC_REG : SPECIAL_REGS))
2.84
2.85 /* A C expression for the number of consecutive hard registers,
2.86 starting at register number REGNO, required to hold a value of mode
2.87 @@ -378,11 +392,11 @@
2.88
2.89 /* The register number of the frame pointer register, which is used to
2.90 access automatic variables in the stack frame. */
2.91 -#define FRAME_POINTER_REGNUM 8
2.92 +#define FRAME_POINTER_REGNUM 16
2.93
2.94 /* The register number of the arg pointer register, which is used to
2.95 access the function's argument list. */
2.96 -#define ARG_POINTER_REGNUM 9
2.97 +#define ARG_POINTER_REGNUM 17
2.98
2.99 /* If the static chain is passed in memory, these macros provide rtx
2.100 giving 'mem' expressions that denote where they are stored.
3.1 --- a/gcc/gcc/config/ggx/ggx.md Mon Aug 18 07:46:30 2008 -0700
3.2 +++ b/gcc/gcc/config/ggx/ggx.md Wed Aug 20 11:54:09 2008 -0700
3.3 @@ -15,58 +15,58 @@
3.4 (define_insn "addsi3"
3.5 [(set (match_operand:SI 0 "register_operand" "=r")
3.6 (plus:SI
3.7 - (match_operand:SI 1 "register_operand" "r")
3.8 + (match_operand:SI 1 "register_operand" "0")
3.9 (match_operand:SI 2 "general_operand" "r")))]
3.10 ""
3.11 - "add.l %0, %1, %2")
3.12 + "add.l %0, %2")
3.13
3.14 (define_insn "subsi3"
3.15 [(set (match_operand:SI 0 "register_operand" "=r")
3.16 (minus:SI
3.17 - (match_operand:SI 1 "register_operand" "r")
3.18 + (match_operand:SI 1 "register_operand" "0")
3.19 (match_operand:SI 2 "general_operand" "r")))]
3.20 ""
3.21 - "sub.l %0, %1, %2")
3.22 + "sub.l %0, %2")
3.23
3.24 (define_insn "mulsi3"
3.25 [(set (match_operand:SI 0 "register_operand" "=r")
3.26 (mult:SI
3.27 - (match_operand:SI 1 "register_operand" "r")
3.28 + (match_operand:SI 1 "register_operand" "0")
3.29 (match_operand:SI 2 "general_operand" "r")))]
3.30 ""
3.31 - "mul.l %0, %1, %2")
3.32 + "mul.l %0, %2")
3.33
3.34 (define_insn "divsi3"
3.35 [(set (match_operand:SI 0 "register_operand" "=r")
3.36 (div:SI
3.37 - (match_operand:SI 1 "register_operand" "r")
3.38 + (match_operand:SI 1 "register_operand" "0")
3.39 (match_operand:SI 2 "general_operand" "r")))]
3.40 ""
3.41 - "div.l %0, %1, %2")
3.42 + "div.l %0, %2")
3.43
3.44 (define_insn "udivsi3"
3.45 [(set (match_operand:SI 0 "register_operand" "=r")
3.46 (udiv:SI
3.47 - (match_operand:SI 1 "register_operand" "r")
3.48 + (match_operand:SI 1 "register_operand" "0")
3.49 (match_operand:SI 2 "general_operand" "r")))]
3.50 ""
3.51 - "udiv.l %0, %1, %2")
3.52 + "udiv.l %0, %2")
3.53
3.54 (define_insn "modsi3"
3.55 [(set (match_operand:SI 0 "register_operand" "=r")
3.56 (mod:SI
3.57 - (match_operand:SI 1 "register_operand" "r")
3.58 + (match_operand:SI 1 "register_operand" "0")
3.59 (match_operand:SI 2 "general_operand" "r")))]
3.60 ""
3.61 - "mod.l %0, %1, %2")
3.62 + "mod.l %0, %2")
3.63
3.64 (define_insn "umodsi3"
3.65 [(set (match_operand:SI 0 "register_operand" "=r")
3.66 (umod:SI
3.67 - (match_operand:SI 1 "register_operand" "r")
3.68 + (match_operand:SI 1 "register_operand" "0")
3.69 (match_operand:SI 2 "general_operand" "r")))]
3.70 ""
3.71 - "umod.l %0, %1, %2")
3.72 + "umod.l %0, %2")
3.73
3.74 ;; -------------------------------------------------------------------------
3.75 ;; Unary arithmetic instructions
3.76 @@ -90,29 +90,29 @@
3.77
3.78 (define_insn "andsi3"
3.79 [(set (match_operand:SI 0 "register_operand" "=r")
3.80 - (and:SI (match_operand:SI 1 "register_operand" "r")
3.81 + (and:SI (match_operand:SI 1 "register_operand" "0")
3.82 (match_operand:SI 2 "register_operand" "r")))]
3.83 ""
3.84 {
3.85 - return "and %0, %1, %2";
3.86 + return "and %0, %2";
3.87 })
3.88
3.89 (define_insn "xorsi3"
3.90 [(set (match_operand:SI 0 "register_operand" "=r")
3.91 - (xor:SI (match_operand:SI 1 "register_operand" "r")
3.92 + (xor:SI (match_operand:SI 1 "register_operand" "0")
3.93 (match_operand:SI 2 "register_operand" "r")))]
3.94 ""
3.95 {
3.96 - return "xor %0, %1, %2";
3.97 + return "xor %0, %2";
3.98 })
3.99
3.100 (define_insn "iorsi3"
3.101 [(set (match_operand:SI 0 "register_operand" "=r")
3.102 - (ior:SI (match_operand:SI 1 "register_operand" "r")
3.103 + (ior:SI (match_operand:SI 1 "register_operand" "0")
3.104 (match_operand:SI 2 "register_operand" "r")))]
3.105 ""
3.106 {
3.107 - return "or %0, %1, %2";
3.108 + return "or %0, %2";
3.109 })
3.110
3.111 ;; -------------------------------------------------------------------------
4.1 --- a/src/gas/ChangeLog.ggx Mon Aug 18 07:46:30 2008 -0700
4.2 +++ b/src/gas/ChangeLog.ggx Wed Aug 20 11:54:09 2008 -0700
4.3 @@ -1,3 +1,9 @@
4.4 +2008-08-20 Anthony Green <green@spindazzle.org>
4.5 +
4.6 + * config/tc-ggx.c (md_assemble): Handle new instruction encodings.
4.7 + (parse_register_operand): Parse register operands from $r6 to
4.8 + $r13.
4.9 +
4.10 2008-03-20 Anthony Green <green@spindazzle.org>
4.11
4.12 * config/tc-ggx.c (md_assemble): Add GGX_F1_A support.
5.1 --- a/src/gas/config/tc-ggx.c Mon Aug 18 07:46:30 2008 -0700
5.2 +++ b/src/gas/config/tc-ggx.c Wed Aug 20 11:54:09 2008 -0700
5.3 @@ -109,11 +109,20 @@
5.4 if (s[1] == 'r')
5.5 {
5.6 reg = s[2] - '0';
5.7 - if ((reg < 0) || (reg > 5))
5.8 + if ((reg < 0) || (reg > 9))
5.9 {
5.10 as_bad ("illegal register number");
5.11 ignore_rest_of_line ();
5.12 return -1;
5.13 + }
5.14 + if (reg == 1)
5.15 + {
5.16 + int r2 = s[3] - '0';
5.17 + if ((r2 >= 0) && (r2 <= 3))
5.18 + {
5.19 + reg = 10 + r2;
5.20 + *ptr += 1;
5.21 + }
5.22 }
5.23 }
5.24 else
5.25 @@ -176,7 +185,7 @@
5.26 switch (opcode->itype)
5.27 {
5.28 case GGX_F1_AB:
5.29 - iword = opcode->opcode << 9;
5.30 + iword = opcode->opcode << 8;
5.31 while (ISSPACE (*op_end))
5.32 op_end++;
5.33 {
5.34 @@ -186,29 +195,7 @@
5.35 as_warn ("expecting comma delimeted register operands");
5.36 op_end++;
5.37 src = parse_register_operand (&op_end);
5.38 - iword += (dest << 6) + (src << 3);
5.39 - while (ISSPACE (*op_end))
5.40 - op_end++;
5.41 - if (*op_end != 0)
5.42 - as_warn ("extra stuff on line ignored");
5.43 - }
5.44 - break;
5.45 - case GGX_F1_ABC:
5.46 - iword = opcode->opcode << 9;
5.47 - while (ISSPACE (*op_end))
5.48 - op_end++;
5.49 - {
5.50 - int a, b, c;
5.51 - a = parse_register_operand (&op_end);
5.52 - if (*op_end != ',')
5.53 - as_warn ("expecting comma delimeted register operands");
5.54 - op_end++;
5.55 - b = parse_register_operand (&op_end);
5.56 - if (*op_end != ',')
5.57 - as_warn ("expecting comma delimeted register operands");
5.58 - op_end++;
5.59 - c = parse_register_operand (&op_end);
5.60 - iword += (a << 6) + (b << 3) + c;
5.61 + iword += (dest << 4) + src;
5.62 while (ISSPACE (*op_end))
5.63 op_end++;
5.64 if (*op_end != 0)
5.65 @@ -216,7 +203,7 @@
5.66 }
5.67 break;
5.68 case GGX_F1_A4:
5.69 - iword = opcode->opcode << 9;
5.70 + iword = opcode->opcode << 8;
5.71 while (ISSPACE (*op_end))
5.72 op_end++;
5.73 {
5.74 @@ -228,7 +215,7 @@
5.75 while (ISSPACE (*op_end))
5.76 op_end++;
5.77
5.78 - iword += (regnum << 6);
5.79 + iword += (regnum << 4);
5.80
5.81 if (*op_end != ',')
5.82 {
5.83 @@ -249,7 +236,7 @@
5.84 }
5.85 break;
5.86 case GGX_F1_4:
5.87 - iword = opcode->opcode << 9;
5.88 + iword = opcode->opcode << 8;
5.89 while (ISSPACE (*op_end))
5.90 op_end++;
5.91 {
5.92 @@ -267,14 +254,14 @@
5.93 }
5.94 break;
5.95 case GGX_F1_NARG:
5.96 - iword = opcode->opcode << 9;
5.97 + iword = opcode->opcode << 8;
5.98 while (ISSPACE (*op_end))
5.99 op_end++;
5.100 if (*op_end != 0)
5.101 as_warn ("extra stuff on line ignored");
5.102 break;
5.103 case GGX_F1_A:
5.104 - iword = opcode->opcode << 9;
5.105 + iword = opcode->opcode << 8;
5.106 while (ISSPACE (*op_end))
5.107 op_end++;
5.108 {
5.109 @@ -284,11 +271,11 @@
5.110 op_end++;
5.111 if (*op_end != 0)
5.112 as_warn ("extra stuff on line ignored");
5.113 - iword += (reg << 6);
5.114 + iword += (reg << 4);
5.115 }
5.116 break;
5.117 case GGX_F1_ABi:
5.118 - iword = opcode->opcode << 9;
5.119 + iword = opcode->opcode << 8;
5.120 while (ISSPACE (*op_end))
5.121 op_end++;
5.122 {
5.123 @@ -312,7 +299,7 @@
5.124 return;
5.125 }
5.126 op_end++;
5.127 - iword += (a << 6) + (b << 3);
5.128 + iword += (a << 4) + b;
5.129 while (ISSPACE (*op_end))
5.130 op_end++;
5.131 if (*op_end != 0)
5.132 @@ -320,7 +307,7 @@
5.133 }
5.134 break;
5.135 case GGX_F1_AiB:
5.136 - iword = opcode->opcode << 9;
5.137 + iword = opcode->opcode << 8;
5.138 while (ISSPACE (*op_end))
5.139 op_end++;
5.140 {
5.141 @@ -344,7 +331,7 @@
5.142 as_warn ("expecting comma delimeted register operands");
5.143 op_end++;
5.144 b = parse_register_operand (&op_end);
5.145 - iword += (a << 6) + (b << 3);
5.146 + iword += (a << 4) + b;
5.147 while (ISSPACE (*op_end))
5.148 op_end++;
5.149 if (*op_end != 0)
5.150 @@ -352,7 +339,7 @@
5.151 }
5.152 break;
5.153 case GGX_F1_4A:
5.154 - iword = opcode->opcode << 9;
5.155 + iword = opcode->opcode << 8;
5.156 while (ISSPACE (*op_end))
5.157 op_end++;
5.158 {
5.159 @@ -383,11 +370,11 @@
5.160 if (*op_end != 0)
5.161 as_warn ("extra stuff on line ignored");
5.162
5.163 - iword += (a << 6);
5.164 + iword += (a << 4);
5.165 }
5.166 break;
5.167 case GGX_F1_ABi4:
5.168 - iword = opcode->opcode << 9;
5.169 + iword = opcode->opcode << 8;
5.170 while (ISSPACE (*op_end))
5.171 op_end++;
5.172 {
5.173 @@ -437,11 +424,11 @@
5.174 if (*op_end != 0)
5.175 as_warn ("extra stuff on line ignored");
5.176
5.177 - iword += (a << 6) + (b << 3);
5.178 + iword += (a << 4) + b;
5.179 }
5.180 break;
5.181 case GGX_F1_AiB4:
5.182 - iword = opcode->opcode << 9;
5.183 + iword = opcode->opcode << 8;
5.184 while (ISSPACE (*op_end))
5.185 op_end++;
5.186 {
5.187 @@ -491,7 +478,7 @@
5.188 if (*op_end != 0)
5.189 as_warn ("extra stuff on line ignored");
5.190
5.191 - iword += (a << 6) + (b << 3);
5.192 + iword += (a << 4) + b;
5.193 }
5.194 break;
5.195 case GGX_F2_NARG:
6.1 --- a/src/include/opcode/ggx.h Mon Aug 18 07:46:30 2008 -0700
6.2 +++ b/src/include/opcode/ggx.h Wed Aug 20 11:54:09 2008 -0700
6.3 @@ -23,7 +23,6 @@
6.4 Some have no arguments (GGX_F1_NARG)
6.5 Some only use the A operand (GGX_F1_A)
6.6 Some use A and B registers (GGX_F1_AB)
6.7 - Some use A, B and C registers (GGX_F1_ABC)
6.8 Some use A and consume a 4 byte immediate value (GGX_F1_A4)
6.9 Some use just a 4 byte immediate value (GGX_F1_4)
6.10 Some use B and an indirect A (GGX_F1_AiB)
6.11 @@ -41,7 +40,7 @@
6.12 #define GGX_F1_NARG 0x100
6.13 #define GGX_F1_A 0x101
6.14 #define GGX_F1_AB 0x102
6.15 -#define GGX_F1_ABC 0x103
6.16 +// #define GGX_F1_ABC 0x103
6.17 #define GGX_F1_A4 0x104
6.18 #define GGX_F1_4 0x105
6.19 #define GGX_F1_AiB 0x106
7.1 --- a/src/opcodes/ChangeLog.ggx Mon Aug 18 07:46:30 2008 -0700
7.2 +++ b/src/opcodes/ChangeLog.ggx Wed Aug 20 11:54:09 2008 -0700
7.3 @@ -1,3 +1,11 @@
7.4 +2008-08-20 Anthony Green <green@redhat.com>
7.5 +
7.6 + * ggx-dis.c (reg_names): Add new registers.
7.7 + (print_insn_ggx): No more three operand instructions.
7.8 + (OP_A, OP_B): Tweak for 4-bit operands.
7.9 + (OP_C): Remove. No more third operand.
7.10 + * ggx-opc.c (ggx_form1_opc_info): Switch to two operand instructions.
7.11 +
7.12 2008-04-12 Anthony Green <green@spindazzle.org>
7.13
7.14 * ggx-opc.c (ggx_form1_opc_info): Add brk.
8.1 --- a/src/opcodes/ggx-dis.c Mon Aug 18 07:46:30 2008 -0700
8.2 +++ b/src/opcodes/ggx-dis.c Wed Aug 20 11:54:09 2008 -0700
8.3 @@ -31,12 +31,12 @@
8.4 static void *stream;
8.5
8.6 /* Macros to extract operands from the instruction word. */
8.7 -#define OP_A(i) ((i >> 6) & 0x7)
8.8 -#define OP_B(i) ((i >> 3) & 0x7)
8.9 -#define OP_C(i) (i & 0x7)
8.10 +#define OP_A(i) ((i >> 4) & 0xf)
8.11 +#define OP_B(i) (i & 0xf)
8.12
8.13 -static const char *reg_names[8] =
8.14 - { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5" };
8.15 +static const char *reg_names[16] =
8.16 + { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
8.17 + "$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
8.18
8.19 int
8.20 print_insn_ggx (bfd_vma addr, struct disassemble_info *info)
8.21 @@ -57,7 +57,7 @@
8.22 if ((iword & (1<<15)) == 0)
8.23 {
8.24 /* Extract the Form 1 opcode. */
8.25 - opcode = &ggx_form1_opc_info[iword >> 9];
8.26 + opcode = &ggx_form1_opc_info[iword >> 8];
8.27 switch (opcode->itype)
8.28 {
8.29 case GGX_F1_NARG:
8.30 @@ -71,12 +71,6 @@
8.31 fpr (stream, "%s\t%s, %s", opcode->name,
8.32 reg_names[OP_A(iword)],
8.33 reg_names[OP_B(iword)]);
8.34 - break;
8.35 - case GGX_F1_ABC:
8.36 - fpr (stream, "%s\t%s, %s, %s", opcode->name,
8.37 - reg_names[OP_A(iword)],
8.38 - reg_names[OP_B(iword)],
8.39 - reg_names[OP_C(iword)]);
8.40 break;
8.41 case GGX_F1_A4:
8.42 {
9.1 --- a/src/opcodes/ggx-opc.c Mon Aug 18 07:46:30 2008 -0700
9.2 +++ b/src/opcodes/ggx-opc.c Wed Aug 20 11:54:09 2008 -0700
9.3 @@ -27,13 +27,12 @@
9.4
9.5 FORM 1 instructions start with a 0 bit...
9.6
9.7 - 0ooooooaaabbbccc
9.8 + 0oooooooaaaabbbb
9.9 0 F
9.10
9.11 - oooooo - form 1 opcode number
9.12 - aaa - operand A
9.13 - bbb - operand B
9.14 - ccc - operand C
9.15 + ooooooo - form 1 opcode number
9.16 + aaaa - operand A
9.17 + bbbb - operand B
9.18
9.19 FORM 2 instructions start with a 1 bit...
9.20
9.21 @@ -51,7 +50,7 @@
9.22 { 0x01, GGX_F1_AB, "mov" },
9.23 { 0x02, GGX_F1_4, "jsra" },
9.24 { 0x03, GGX_F1_NARG, "ret" },
9.25 - { 0x04, GGX_F1_ABC, "add.l" },
9.26 + { 0x04, GGX_F1_AB, "add.l" },
9.27 { 0x05, GGX_F1_AB, "push" },
9.28 { 0x06, GGX_F1_AB, "pop" },
9.29 { 0x07, GGX_F1_A4, "lda.l" },
9.30 @@ -84,21 +83,21 @@
9.31 { 0x22, GGX_F1_AiB, "st.s" },
9.32 { 0x23, GGX_F1_4A, "sta.s" },
9.33 { 0x24, GGX_F1_A, "jmp" },
9.34 - { 0x25, GGX_F1_ABC, "and" },
9.35 + { 0x25, GGX_F1_AB, "and" },
9.36 { 0x26, GGX_F1_AB, "lshr" },
9.37 { 0x27, GGX_F1_AB, "ashl" },
9.38 - { 0x28, GGX_F1_ABC, "sub.l" },
9.39 + { 0x28, GGX_F1_AB, "sub.l" },
9.40 { 0x29, GGX_F1_AB, "neg" },
9.41 - { 0x2a, GGX_F1_ABC, "or" },
9.42 + { 0x2a, GGX_F1_AB, "or" },
9.43 { 0x2b, GGX_F1_AB, "not" },
9.44 { 0x2c, GGX_F1_AB, "ashr" },
9.45 - { 0x2d, GGX_F1_ABC, "xor" },
9.46 - { 0x2e, GGX_F1_ABC, "mul.l" },
9.47 + { 0x2d, GGX_F1_AB, "xor" },
9.48 + { 0x2e, GGX_F1_AB, "mul.l" },
9.49 { 0x2f, GGX_F1_4, "swi" },
9.50 - { 0x30, GGX_F1_ABC, "div.l" },
9.51 - { 0x31, GGX_F1_ABC, "udiv.l" },
9.52 - { 0x32, GGX_F1_ABC, "mod.l" },
9.53 - { 0x33, GGX_F1_ABC, "umod.l" },
9.54 + { 0x30, GGX_F1_AB, "div.l" },
9.55 + { 0x31, GGX_F1_AB, "udiv.l" },
9.56 + { 0x32, GGX_F1_AB, "mod.l" },
9.57 + { 0x33, GGX_F1_AB, "umod.l" },
9.58 { 0x34, GGX_F1_NARG, "brk" },
9.59 { 0x35, GGX_F1_NARG, "bad" },
9.60 { 0x36, GGX_F1_NARG, "bad" },
10.1 --- a/src/sim/ggx/ChangeLog Mon Aug 18 07:46:30 2008 -0700
10.2 +++ b/src/sim/ggx/ChangeLog Wed Aug 20 11:54:09 2008 -0700
10.3 @@ -1,3 +1,12 @@
10.4 +2008-08-20 Anthony Green <green@spindazzle.org>
10.5 +
10.6 + * interp.c (TRACE): Add new tracing infrastructure.
10.7 + (sim_resume): Use it.
10.8 + (reg_names): Add new registers.
10.9 + (NUM_GGX_REGS): New registers.
10.10 + (PC_REGNO): New registers.
10.11 + (sim_resume): New instruction encodings.
10.12 +
10.13 2008-08-16 Anthony Green <green@spindazzle.org>
10.14
10.15 * interp.c (sim_resume): Add SYS_read, and fix SYS_open and SYS_write.
11.1 --- a/src/sim/ggx/interp.c Mon Aug 18 07:46:30 2008 -0700
11.2 +++ b/src/sim/ggx/interp.c Wed Aug 20 11:54:09 2008 -0700
11.3 @@ -82,8 +82,9 @@
11.4 }
11.5
11.6 /* ggx register names. */
11.7 -static const char *reg_names[8] =
11.8 - { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5" };
11.9 +static const char *reg_names[16] =
11.10 + { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
11.11 + "$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
11.12
11.13 /* The machine state.
11.14
11.15 @@ -94,8 +95,8 @@
11.16 data in native order improves the performance of the simulator.
11.17 Simulation speed is deemed more important. */
11.18
11.19 -#define NUM_GGX_REGS 9 /* Including PC */
11.20 -#define PC_REGNO 8
11.21 +#define NUM_GGX_REGS 17 /* Including PC */
11.22 +#define PC_REGNO 16
11.23
11.24 /* The ordering of the ggx_regset structure is matched in the
11.25 gdb/config/ggx/tm-ggx.h file in the REGISTER_NAMES macro. */
11.26 @@ -385,6 +386,7 @@
11.27 return hflags;
11.28 }
11.29
11.30 +#define TRACE(str) if (tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);
11.31
11.32 static int tracing = 0;
11.33
11.34 @@ -407,12 +409,6 @@
11.35 /* Run instructions here. */
11.36 do
11.37 {
11.38 - if (tracing)
11.39 - {
11.40 - fwrite(&pc, 4, 1, tracefile);
11.41 - fwrite(cpu.asints, NUM_GGX_REGS + 1 + 2, 4, tracefile);
11.42 - }
11.43 -
11.44 opc = pc;
11.45
11.46 /* Fetch the instruction at pc. */
11.47 @@ -429,13 +425,13 @@
11.48 else
11.49 {
11.50 /* This is a Form 1 instruction. */
11.51 - int opcode = inst >> 9;
11.52 + int opcode = inst >> 8;
11.53 switch (opcode)
11.54 {
11.55 case 0x00: /* ldi.l (immediate) */
11.56 {
11.57 - int reg = (inst >> 6) & 0x7;
11.58 -
11.59 + int reg = (inst >> 4) & 0xf;
11.60 + TRACE("ldi.l");
11.61 unsigned int val = EXTRACT_WORD(&(memory[pc + 2]));
11.62 cpu.asregs.regs[reg] = val;
11.63 pc += 4;
11.64 @@ -443,8 +439,9 @@
11.65 break;
11.66 case 0x01: /* mov (register-to-register) */
11.67 {
11.68 - int dest = (inst >> 6) & 0x7;
11.69 - int src = (inst >> 3) & 0x7;
11.70 + int dest = (inst >> 4) & 0xf;
11.71 + int src = (inst ) & 0xf;
11.72 + TRACE("mov");
11.73 cpu.asregs.regs[dest] = cpu.asregs.regs[src];
11.74 }
11.75 break;
11.76 @@ -452,7 +449,7 @@
11.77 {
11.78 unsigned int fn = EXTRACT_WORD(&(memory[pc + 2]));
11.79 unsigned int sp = cpu.asregs.regs[1];
11.80 -
11.81 + TRACE("jsra");
11.82 /* Save a slot for the static chain. */
11.83 sp -= 4;
11.84
11.85 @@ -473,6 +470,8 @@
11.86 case 0x03: /* ret */
11.87 {
11.88 unsigned int sp = cpu.asregs.regs[0];
11.89 +
11.90 + TRACE("ret");
11.91
11.92 /* Pop the frame pointer. */
11.93 cpu.asregs.regs[0] = rlat (opc, sp);
11.94 @@ -491,69 +490,76 @@
11.95 break;
11.96 case 0x04: /* add.l */
11.97 {
11.98 - int a = (inst >> 6) & 0x7;
11.99 - int b = (inst >> 3) & 0x7;
11.100 - int c = inst & 0x7;
11.101 + int a = (inst >> 4) & 0xf;
11.102 + int b = inst & 0xf;
11.103 + unsigned av = cpu.asregs.regs[a];
11.104 unsigned bv = cpu.asregs.regs[b];
11.105 - unsigned cv = cpu.asregs.regs[c];
11.106 - cpu.asregs.regs[a] = bv + cv;
11.107 + TRACE("add.l");
11.108 + cpu.asregs.regs[a] = av + bv;
11.109 }
11.110 break;
11.111 case 0x05: /* push */
11.112 {
11.113 - int a = (inst >> 6) & 0x7;
11.114 - int b = (inst >> 3) & 0x7;
11.115 + int a = (inst >> 4) & 0xf;
11.116 + int b = inst & 0xf;
11.117 int sp = cpu.asregs.regs[a] - 4;
11.118 + TRACE("push");
11.119 wlat (opc, sp, cpu.asregs.regs[b]);
11.120 cpu.asregs.regs[a] = sp;
11.121 }
11.122 break;
11.123 case 0x06: /* pop */
11.124 {
11.125 - int a = (inst >> 6) & 0x7;
11.126 - int b = (inst >> 3) & 0x7;
11.127 + int a = (inst >> 4) & 0xf;
11.128 + int b = inst & 0xf;
11.129 int sp = cpu.asregs.regs[a];
11.130 + TRACE("pop");
11.131 cpu.asregs.regs[b] = rlat (opc, sp);
11.132 cpu.asregs.regs[a] = sp + 4;
11.133 }
11.134 break;
11.135 case 0x07: /* lda.l */
11.136 {
11.137 - int reg = (inst >> 6) & 0x7;
11.138 + int reg = (inst >> 4) & 0xf;
11.139 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
11.140 + TRACE("lda.l");
11.141 cpu.asregs.regs[reg] = rlat (opc, addr);
11.142 pc += 4;
11.143 }
11.144 break;
11.145 case 0x08: /* sta.l */
11.146 {
11.147 - int reg = (inst >> 6) & 0x7;
11.148 + int reg = (inst >> 4) & 0xf;
11.149 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
11.150 + TRACE("sta.l");
11.151 wlat (opc, addr, cpu.asregs.regs[reg]);
11.152 pc += 4;
11.153 }
11.154 break;
11.155 case 0x09: /* ld.l (register indirect) */
11.156 {
11.157 - int src = (inst >> 3) & 0x7;
11.158 - int dest = (inst >> 6) & 0x7;
11.159 + int src = inst & 0xf;
11.160 + int dest = (inst >> 4) & 0xf;
11.161 int xv;
11.162 + TRACE("ld.l");
11.163 xv = cpu.asregs.regs[src];
11.164 cpu.asregs.regs[dest] = rlat (opc, xv);
11.165 }
11.166 break;
11.167 case 0x0a: /* st.l */
11.168 {
11.169 - int dest = (inst >> 6) & 0x7;
11.170 - int val = (inst >> 3) & 0x7;
11.171 + int dest = (inst >> 4) & 0xf;
11.172 + int val = inst & 0xf;
11.173 + TRACE("st.l");
11.174 wlat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
11.175 }
11.176 break;
11.177 case 0x0b: /* ldo.l */
11.178 {
11.179 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
11.180 - int a = (inst >> 6) & 0x7;
11.181 - int b = (inst >> 3) & 0x7;
11.182 + int a = (inst >> 4) & 0xf;
11.183 + int b = inst & 0xf;
11.184 + TRACE("ldo.l");
11.185 addr += cpu.asregs.regs[b];
11.186 cpu.asregs.regs[a] = rlat(opc, addr);
11.187 pc += 4;
11.188 @@ -562,8 +568,9 @@
11.189 case 0x0c: /* sto.w */
11.190 {
11.191 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
11.192 - int a = (inst >> 6) & 0x7;
11.193 - int b = (inst >> 3) & 0x7;
11.194 + int a = (inst >> 4) & 0xf;
11.195 + int b = inst & 0xf;
11.196 + TRACE("sto.w");
11.197 addr += cpu.asregs.regs[a];
11.198 wlat(opc, addr, cpu.asregs.regs[b]);
11.199 pc += 4;
11.200 @@ -571,11 +578,13 @@
11.201 break;
11.202 case 0x0d: /* cmp */
11.203 {
11.204 - int a = (inst >> 6) & 0x7;
11.205 - int b = (inst >> 3) & 0x7;
11.206 + int a = (inst >> 4) & 0xf;
11.207 + int b = inst & 0xf;
11.208 int cc = 0;
11.209 int va = cpu.asregs.regs[a];
11.210 int vb = cpu.asregs.regs[b];
11.211 +
11.212 + TRACE("cmp");
11.213
11.214 if (va == vb)
11.215 cc = CC_EQ;
11.216 @@ -593,6 +602,7 @@
11.217 case 0x0e: /* beq */
11.218 {
11.219 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.220 + TRACE("beq");
11.221 if (cpu.asregs.cc & CC_EQ)
11.222 {
11.223 pc = tgt - 2;
11.224 @@ -604,6 +614,7 @@
11.225 case 0x0f: /* bne */
11.226 {
11.227 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.228 + TRACE("bne");
11.229 if (! (cpu.asregs.cc & CC_EQ))
11.230 {
11.231 pc = tgt - 2;
11.232 @@ -615,6 +626,7 @@
11.233 case 0x10: /* blt */
11.234 {
11.235 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.236 + TRACE("blt");
11.237 if (cpu.asregs.cc & CC_LT)
11.238 {
11.239 pc = tgt - 2;
11.240 @@ -626,6 +638,7 @@
11.241 case 0x11: /* bgt */
11.242 {
11.243 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.244 + TRACE("bgt");
11.245 if (cpu.asregs.cc & CC_GT)
11.246 {
11.247 pc = tgt - 2;
11.248 @@ -637,6 +650,7 @@
11.249 case 0x12: /* bltu */
11.250 {
11.251 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.252 + TRACE("bltu");
11.253 if (cpu.asregs.cc & CC_LTU)
11.254 {
11.255 pc = tgt - 2;
11.256 @@ -648,6 +662,7 @@
11.257 case 0x13: /* bgtu */
11.258 {
11.259 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.260 + TRACE("bgtu");
11.261 if (cpu.asregs.cc & CC_GTU)
11.262 {
11.263 pc = tgt - 2;
11.264 @@ -659,6 +674,7 @@
11.265 case 0x14: /* bge */
11.266 {
11.267 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.268 + TRACE("bge");
11.269 if ((cpu.asregs.cc & CC_GT) || (cpu.asregs.cc & CC_EQ))
11.270 {
11.271 pc = tgt - 2;
11.272 @@ -670,6 +686,7 @@
11.273 case 0x15: /* ble */
11.274 {
11.275 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.276 + TRACE("ble");
11.277 if ((cpu.asregs.cc & CC_LT) || (cpu.asregs.cc & CC_EQ))
11.278 {
11.279 pc = tgt - 2;
11.280 @@ -681,6 +698,7 @@
11.281 case 0x16: /* bgeu */
11.282 {
11.283 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.284 + TRACE("bgeu");
11.285 if ((cpu.asregs.cc & CC_GTU) || (cpu.asregs.cc & CC_EQ))
11.286 {
11.287 pc = tgt - 2;
11.288 @@ -692,6 +710,7 @@
11.289 case 0x17: /* bleu */
11.290 {
11.291 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.292 + TRACE("bleu");
11.293 if ((cpu.asregs.cc & CC_LTU) || (cpu.asregs.cc & CC_EQ))
11.294 {
11.295 pc = tgt - 2;
11.296 @@ -702,8 +721,10 @@
11.297 break;
11.298 case 0x18: /* jsr */
11.299 {
11.300 - unsigned int fn = cpu.asregs.regs[(inst >> 6) & 0x7];
11.301 + unsigned int fn = cpu.asregs.regs[(inst >> 4) & 0xf];
11.302 unsigned int sp = cpu.asregs.regs[1];
11.303 +
11.304 + TRACE("jsr");
11.305
11.306 /* Save a slot for the static chain. */
11.307 sp -= 4;
11.308 @@ -725,196 +746,214 @@
11.309 case 0x19: /* jmpa */
11.310 {
11.311 unsigned int tgt = EXTRACT_WORD(&memory[pc+2]);
11.312 + TRACE("jmpa");
11.313 pc = tgt - 2;
11.314 }
11.315 break;
11.316 case 0x1a: /* ldi.b (immediate) */
11.317 {
11.318 - int reg = (inst >> 6) & 0x7;
11.319 + int reg = (inst >> 4) & 0xf;
11.320
11.321 unsigned int val = EXTRACT_WORD(&(memory[pc + 2]));
11.322 + TRACE("ldi.b");
11.323 cpu.asregs.regs[reg] = val;
11.324 pc += 4;
11.325 }
11.326 break;
11.327 case 0x1b: /* ld.b (register indirect) */
11.328 {
11.329 - int src = (inst >> 3) & 0x7;
11.330 - int dest = (inst >> 6) & 0x7;
11.331 + int src = inst & 0xf;
11.332 + int dest = (inst >> 4) & 0xf;
11.333 int xv;
11.334 + TRACE("ld.b");
11.335 xv = cpu.asregs.regs[src];
11.336 cpu.asregs.regs[dest] = rbat (opc, xv);
11.337 }
11.338 break;
11.339 case 0x1c: /* lda.b */
11.340 {
11.341 - int reg = (inst >> 6) & 0x7;
11.342 + int reg = (inst >> 4) & 0xf;
11.343 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
11.344 + TRACE("lda.b");
11.345 cpu.asregs.regs[reg] = rbat (opc, addr);
11.346 pc += 4;
11.347 }
11.348 break;
11.349 case 0x1d: /* st.b */
11.350 {
11.351 - int dest = (inst >> 6) & 0x7;
11.352 - int val = (inst >> 3) & 0x7;
11.353 + int dest = (inst >> 4) & 0xf;
11.354 + int val = inst & 0xf;
11.355 + TRACE("st.b");
11.356 wbat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
11.357 }
11.358 break;
11.359 case 0x1e: /* sta.b */
11.360 {
11.361 - int reg = (inst >> 6) & 0x7;
11.362 + int reg = (inst >> 4) & 0xf;
11.363 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
11.364 + TRACE("sta.b");
11.365 wbat (opc, addr, cpu.asregs.regs[reg]);
11.366 pc += 4;
11.367 }
11.368 break;
11.369 case 0x1f: /* ldi.s (immediate) */
11.370 {
11.371 - int reg = (inst >> 6) & 0x7;
11.372 + int reg = (inst >> 4) & 0xf;
11.373
11.374 unsigned int val = EXTRACT_WORD(&(memory[pc + 2]));
11.375 + TRACE("ldi.s");
11.376 cpu.asregs.regs[reg] = val;
11.377 pc += 4;
11.378 }
11.379 break;
11.380 case 0x20: /* ld.s (register indirect) */
11.381 {
11.382 - int src = (inst >> 3) & 0x7;
11.383 - int dest = (inst >> 6) & 0x7;
11.384 + int src = inst & 0xf;
11.385 + int dest = (inst >> 4) & 0xf;
11.386 int xv;
11.387 + TRACE("ld.s");
11.388 xv = cpu.asregs.regs[src];
11.389 cpu.asregs.regs[dest] = rsat (opc, xv);
11.390 }
11.391 break;
11.392 case 0x21: /* lda.s */
11.393 {
11.394 - int reg = (inst >> 6) & 0x7;
11.395 + int reg = (inst >> 4) & 0xf;
11.396 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
11.397 + TRACE("lda.s");
11.398 cpu.asregs.regs[reg] = rsat (opc, addr);
11.399 pc += 4;
11.400 }
11.401 break;
11.402 case 0x22: /* st.s */
11.403 {
11.404 - int dest = (inst >> 6) & 0x7;
11.405 - int val = (inst >> 3) & 0x7;
11.406 + int dest = (inst >> 4) & 0xf;
11.407 + int val = inst & 0xf;
11.408 + TRACE("st.s");
11.409 wsat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
11.410 }
11.411 break;
11.412 case 0x23: /* sta.s */
11.413 {
11.414 - int reg = (inst >> 6) & 0x7;
11.415 + int reg = (inst >> 4) & 0xf;
11.416 unsigned int addr = EXTRACT_WORD(&memory[pc+2]);
11.417 + TRACE("sta.s");
11.418 wsat (opc, addr, cpu.asregs.regs[reg]);
11.419 pc += 4;
11.420 }
11.421 break;
11.422 case 0x24: /* jmp */
11.423 {
11.424 - int reg = (inst >> 6) & 0x7;
11.425 + int reg = (inst >> 4) & 0xf;
11.426 + TRACE("jmp");
11.427 pc = cpu.asregs.regs[reg] - 2;
11.428 }
11.429 break;
11.430 case 0x25: /* and */
11.431 {
11.432 - int a = (inst >> 6) & 0x7;
11.433 - int b = (inst >> 3) & 0x7;
11.434 - int c = inst & 0x7;
11.435 - int bv, cv;
11.436 + int a = (inst >> 4) & 0xf;
11.437 + int b = inst & 0xf;
11.438 + int av, bv;
11.439 + TRACE("and");
11.440 + av = cpu.asregs.regs[a];
11.441 bv = cpu.asregs.regs[b];
11.442 - cv = cpu.asregs.regs[c];
11.443 - cpu.asregs.regs[a] = bv & cv;
11.444 + cpu.asregs.regs[a] = av & bv;
11.445 }
11.446 break;
11.447 case 0x26: /* lshr */
11.448 {
11.449 - int a = (inst >> 6) & 0x7;
11.450 - int b = (inst >> 3) & 0x7;
11.451 + int a = (inst >> 4) & 0xf;
11.452 + int b =